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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
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2.2. Creating RX-Only or TX-Only Designs
For advanced users, you can use the DisplayPort design to create a TX- or RX-only design.
Figure 7. Components Required for RX-Only or TX-Only Design
To use RX- or TX-only components:
- Remove the irrelevant blocks from the design.
- Edit the config.h file in the software folder to specify if DP_SUPPORT_RX and DP_SUPPORT_TX is 1 or 0. The default setting for both parameters is 1.
- For TX-only design, set DP_SUPPORT_RX and BITEC_RX_GPUMODE to 0.
- For RX-only design, set DP_SUPPORT_TX to 0.
User Requirement | Preserve | Remove | Add |
---|---|---|---|
DisplayPort RX Only | RX PHY Top; Core System consists of:
|
|
Video Processing IP |
DisplayPort TX Only | TX PHY Top; Core System consists of:
|
|
Video Pattern Generator |