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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
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3.4.3.1.3. hdcp2x_rx_kmem.v file
For hdcp2x_rx_kmem.v file
- To identify the correct HDCP2 RX DCP key file for hdcp2x_rx_kmem.v, make sure the first 4 bytes of the file are “0x00, 0x00, 0x00, 0x02”.
- The keys in the DCP key files are in little-endian format
Figure 19. Byte mapping from HDCP2 RX DCP key file into hdcp2x_rx_kmem.v
Figure below shows the exact byte mapping from HDCP2 RX DCP key file into hdcp2x_rx_kmem.v
Note: The byte number displays in below format:
- Key size in bytes * key number + byte number in current row + constant offset + row size in bytes * row number
- 862*n indicates that each key set has 862 bytes.
- 16*y indicates that each row has 16 bytes. There is an exception in cert_rx_prod where ROW 32 has only 10 bytes.
Figure 20. HDCP2 RX DCP key file filling with junk values
Figure 21. Wire Arrays of hdcp2x_rx_kmem.v
This figure shows the wire arrays for hdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, and lc128_prod) map to the example of HDCP2 RX DCP key file in Figure 20