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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
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3.4.4. Compile the Design
After you include your own plain HDCP production keys in the FPGA or program the encrypted HDCP production keys to the EEPROM, you can now compile the design.
- Launch the Intel® Quartus® Prime Pro Edition software and open <project directory>/quartus/s10_dp_demo.qpf.
Note: To support all Bitec DisplayPort FMC daughter card revisions, the design example top level RTL file at <project directory>/rtl/s10_dp_demo.v and the software config.h file include a local parameter for you to select the FMC revision. The default value is 1. If the config.h file is updated, you must run build_sw_hdcp.sh in the script folder before compiling the Intel® Quartus® Prime project to ensure the software is effective.
- Click Processing > Start Compilation.