AN 835: PAM4 Signaling Fundamentals

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ID 683852
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. CEI-56G-MR Transmitter 3. CEI-56G-MR-PAM4 Interface Details 4. CEI-56G-MR-PAM4 Receiver 5. PAM4 Link Case Study 6. Medium Reach (MR) PAM4 System Design Study 7. Glossary and Acronyms 8. References 9. Document Revision History for AN 835: PAM4 Signaling Fundamentals
1. Introduction x
1.1. NRZ Fundamentals 1.2. Standards Using PAM4 Coding Scheme 1.3. CEI-56G Interconnect Reaches and Application Distances
1.3. CEI-56G Interconnect Reaches and Application Distances x
1.3.1. VSR (Very Short Reach) Chip-to-Module 1.3.2. MR (Mid-Range Reach) - Chip to Chip Within a PCBA 1.3.3. LR (Long Reach) - Chip to Chip Across a Backplane/Midplane or a Cable
2. CEI-56G-MR Transmitter x
2.1. Naming Conventions 2.2. Eye Height (EH6) and Eye Width (EW6) 2.3. Eye Linearity 2.4. Electrical Characteristics 2.5. PAM4 Jitter Methodology 2.6. TX Pre-Emphasis Method
2.4. Electrical Characteristics x
2.4.1. Transmitter Characteristics 2.4.2. Transmitter Return Loss 2.4.3. Transmitter Linearity (RLM) 2.4.4. Signal-to-Noise-and-Distortion Ratio (SNDR)
3. CEI-56G-MR-PAM4 Interface Details x
3.1. COM Introduction 3.2. Normative Channel Specification COM 3.3. Informative Channel Insertion Loss 3.4. Informative Channel Return Loss
3.1. COM Introduction x
3.1.1. Backplane Measurements
4. CEI-56G-MR-PAM4 Receiver x
4.1. Challenges in Analyzing PAM4 Signals 4.2. PAM4 Receiver Architecture 4.3. Equalization Technique 4.4. CEI-56G-MR-PAM4 Receiver Details
4.2. PAM4 Receiver Architecture x
4.2.1. Analog vs. Digital Receiver 4.2.2. Slicer 4.2.3. Clock and Data Recovery (CDR)
4.4. CEI-56G-MR-PAM4 Receiver Details x
4.4.1. Electrical Characteristics 4.4.2. Receiver Input Return Loss 4.4.3. Receiver Interference Tolerance 4.4.4. Receiver Jitter Tolerance
5. PAM4 Link Case Study x
5.1. OIF_Stressed 5.2. OIF_Compliant
5.1. OIF_Stressed x
5.1.1. Channel Characteristics 5.1.2. OIF_Stressed PAM4 Link Simulation with the Advanced Link Analyzer
5.2. OIF_Compliant x
5.2.1. Channel Characteristics 5.2.2. OIF_Compliant PAM4 Link Simulation with the Advanced Link Analyzer
6. Medium Reach (MR) PAM4 System Design Study x
6.1. System Power 6.2. System Cost 6.3. Board Space 6.4. Conclusion
1. Introduction
2. CEI-56G-MR Transmitter
3. CEI-56G-MR-PAM4 Interface Details
4. CEI-56G-MR-PAM4 Receiver
5. PAM4 Link Case Study
6. Medium Reach (MR) PAM4 System Design Study
7. Glossary and Acronyms
8. References
9. Document Revision History for AN 835: PAM4 Signaling Fundamentals

1.2. Standards Using PAM4 Coding Scheme

Protocol names typically include information about protocol characteristics such as data rate and transmission media. For example, 400GBASE-CR8 is an 8-lane protocol that can achieve a 400 Gbps data rate (with each lane running at 53.125 Gbps). The CR8 part of the name means that signals are traveling through 8 lanes of copper cable.

Figure 4. Sample of a Protocol Name and Available Options

In many electrical interface standards such as the Attachment Unit Interface (AUI), the data rate can be derived from the roman numerals in the protocol names:

Table 1.  Roman Numerals
Symbol I V X L C D M
Value 1 5 10 50 100 500 1000

By decoding the roman numerals in the protocol names, XAUI has a 10 Gbps data rate, CAUI has a 100 Gbps data rate and CDAUI has a 400 Gbps data rate .

Note: If a smaller number appears before a larger number, it is subtracted from the larger number. For example, CDAUI has a data rate of D-C=500-100=400 Gbps. Conversely, if a larger number appears before a smaller number, it is added to the smaller number.

Many standards (such as 400GBASE-SR16) use the PAM4 coding scheme. This 400-Gbps interface uses the Short Reach 100-meter distance optical media protocol. It uses the QSFP-DD pluggable module. The electrical interface is 400GUI-16 or 400GUI-8, which means each lane operates at 26.5625 Gbps or 53.125 Gbps.

200GBASE-KR4 is a standard for a 200 Gbps backplane with four lanes running at a 53.125 Gbps lane rate. It reaches a distance of 0.5 to 1 meter.

100GBASE-CR2 is a 100 Gbps, 3-meter distance protocol using copper cables as media with a 53.125 Gbps lane rate. 100GBASE-CR2 is used in the rack between the server and the top-of-rack Ethernet switch, or between the appliance, router, switch, and server. It uses QSFP56, QSFPDD as the pluggable module.

The exact data rate for the PAM4 signal is determined as follows:

Equation 2. Data Rate per Lane

Level Two Title