AN 835: PAM4 Signaling Fundamentals

Download PDF
ID 683852
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. CEI-56G-MR Transmitter 3. CEI-56G-MR-PAM4 Interface Details 4. CEI-56G-MR-PAM4 Receiver 5. PAM4 Link Case Study 6. Medium Reach (MR) PAM4 System Design Study 7. Glossary and Acronyms 8. References 9. Document Revision History for AN 835: PAM4 Signaling Fundamentals
1. Introduction x
1.1. NRZ Fundamentals 1.2. Standards Using PAM4 Coding Scheme 1.3. CEI-56G Interconnect Reaches and Application Distances
1.3. CEI-56G Interconnect Reaches and Application Distances x
1.3.1. VSR (Very Short Reach) Chip-to-Module 1.3.2. MR (Mid-Range Reach) - Chip to Chip Within a PCBA 1.3.3. LR (Long Reach) - Chip to Chip Across a Backplane/Midplane or a Cable
2. CEI-56G-MR Transmitter x
2.1. Naming Conventions 2.2. Eye Height (EH6) and Eye Width (EW6) 2.3. Eye Linearity 2.4. Electrical Characteristics 2.5. PAM4 Jitter Methodology 2.6. TX Pre-Emphasis Method
2.4. Electrical Characteristics x
2.4.1. Transmitter Characteristics 2.4.2. Transmitter Return Loss 2.4.3. Transmitter Linearity (RLM) 2.4.4. Signal-to-Noise-and-Distortion Ratio (SNDR)
3. CEI-56G-MR-PAM4 Interface Details x
3.1. COM Introduction 3.2. Normative Channel Specification COM 3.3. Informative Channel Insertion Loss 3.4. Informative Channel Return Loss
3.1. COM Introduction x
3.1.1. Backplane Measurements
4. CEI-56G-MR-PAM4 Receiver x
4.1. Challenges in Analyzing PAM4 Signals 4.2. PAM4 Receiver Architecture 4.3. Equalization Technique 4.4. CEI-56G-MR-PAM4 Receiver Details
4.2. PAM4 Receiver Architecture x
4.2.1. Analog vs. Digital Receiver 4.2.2. Slicer 4.2.3. Clock and Data Recovery (CDR)
4.4. CEI-56G-MR-PAM4 Receiver Details x
4.4.1. Electrical Characteristics 4.4.2. Receiver Input Return Loss 4.4.3. Receiver Interference Tolerance 4.4.4. Receiver Jitter Tolerance
5. PAM4 Link Case Study x
5.1. OIF_Stressed 5.2. OIF_Compliant
5.1. OIF_Stressed x
5.1.1. Channel Characteristics 5.1.2. OIF_Stressed PAM4 Link Simulation with the Advanced Link Analyzer
5.2. OIF_Compliant x
5.2.1. Channel Characteristics 5.2.2. OIF_Compliant PAM4 Link Simulation with the Advanced Link Analyzer
6. Medium Reach (MR) PAM4 System Design Study x
6.1. System Power 6.2. System Cost 6.3. Board Space 6.4. Conclusion
1. Introduction
2. CEI-56G-MR Transmitter
3. CEI-56G-MR-PAM4 Interface Details
4. CEI-56G-MR-PAM4 Receiver
5. PAM4 Link Case Study
6. Medium Reach (MR) PAM4 System Design Study
7. Glossary and Acronyms
8. References
9. Document Revision History for AN 835: PAM4 Signaling Fundamentals

2.4.4. Signal-to-Noise-and-Distortion Ratio (SNDR)

SNDR uses linear fit pulse response (p(k)) and linear fit error (e(k)), which is the difference between the actual transmitter output signal and the ideal signal. SNDR is the variation between the ideal signal and the measured signal for a specified number of measurements. It is calculated using p(k) and e(k). As shown in the following equation, where pmax is the maximum value of p(k), sigmae is the standard deviation of e(k). sigman is an average number of 4 measurements of RMS deviation of the PAM4 voltage levels.

Equation 10. Signal-to-Noise-and-Distortion Ratio

SNDR must be at a minimum 31 dB according to the OIF-56G-MR transmitter specification.

SNDR is measured at the transmitter output with transmitters on all lanes enabled and transmitting the QPRBS13-CEI pattern, with at least 14 symbol periods of delay between each lane and with identical transmit equalizer settings.

Level Two Title