AN 835: PAM4 Signaling Fundamentals

Download PDF
ID 683852
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. CEI-56G-MR Transmitter 3. CEI-56G-MR-PAM4 Interface Details 4. CEI-56G-MR-PAM4 Receiver 5. PAM4 Link Case Study 6. Medium Reach (MR) PAM4 System Design Study 7. Glossary and Acronyms 8. References 9. Document Revision History for AN 835: PAM4 Signaling Fundamentals
1. Introduction x
1.1. NRZ Fundamentals 1.2. Standards Using PAM4 Coding Scheme 1.3. CEI-56G Interconnect Reaches and Application Distances
1.3. CEI-56G Interconnect Reaches and Application Distances x
1.3.1. VSR (Very Short Reach) Chip-to-Module 1.3.2. MR (Mid-Range Reach) - Chip to Chip Within a PCBA 1.3.3. LR (Long Reach) - Chip to Chip Across a Backplane/Midplane or a Cable
2. CEI-56G-MR Transmitter x
2.1. Naming Conventions 2.2. Eye Height (EH6) and Eye Width (EW6) 2.3. Eye Linearity 2.4. Electrical Characteristics 2.5. PAM4 Jitter Methodology 2.6. TX Pre-Emphasis Method
2.4. Electrical Characteristics x
2.4.1. Transmitter Characteristics 2.4.2. Transmitter Return Loss 2.4.3. Transmitter Linearity (RLM) 2.4.4. Signal-to-Noise-and-Distortion Ratio (SNDR)
3. CEI-56G-MR-PAM4 Interface Details x
3.1. COM Introduction 3.2. Normative Channel Specification COM 3.3. Informative Channel Insertion Loss 3.4. Informative Channel Return Loss
3.1. COM Introduction x
3.1.1. Backplane Measurements
4. CEI-56G-MR-PAM4 Receiver x
4.1. Challenges in Analyzing PAM4 Signals 4.2. PAM4 Receiver Architecture 4.3. Equalization Technique 4.4. CEI-56G-MR-PAM4 Receiver Details
4.2. PAM4 Receiver Architecture x
4.2.1. Analog vs. Digital Receiver 4.2.2. Slicer 4.2.3. Clock and Data Recovery (CDR)
4.4. CEI-56G-MR-PAM4 Receiver Details x
4.4.1. Electrical Characteristics 4.4.2. Receiver Input Return Loss 4.4.3. Receiver Interference Tolerance 4.4.4. Receiver Jitter Tolerance
5. PAM4 Link Case Study x
5.1. OIF_Stressed 5.2. OIF_Compliant
5.1. OIF_Stressed x
5.1.1. Channel Characteristics 5.1.2. OIF_Stressed PAM4 Link Simulation with the Advanced Link Analyzer
5.2. OIF_Compliant x
5.2.1. Channel Characteristics 5.2.2. OIF_Compliant PAM4 Link Simulation with the Advanced Link Analyzer
6. Medium Reach (MR) PAM4 System Design Study x
6.1. System Power 6.2. System Cost 6.3. Board Space 6.4. Conclusion
1. Introduction
2. CEI-56G-MR Transmitter
3. CEI-56G-MR-PAM4 Interface Details
4. CEI-56G-MR-PAM4 Receiver
5. PAM4 Link Case Study
6. Medium Reach (MR) PAM4 System Design Study
7. Glossary and Acronyms
8. References
9. Document Revision History for AN 835: PAM4 Signaling Fundamentals

3.1. COM Introduction

The Figure of Merit (FOM) of one specific channel, which is regulated by the COM specification, is fixed no matter what transceiver is used. This is because the FOM parameter describes the quality of a channel. FOM is calculated using S-parameters: insertion loss, insertion loss deviation, return loss, integrated crosstalk noise and a number of coefficients that are based on the specific standard. The MR coefficients are described in Table 8.

Table 8.  FOM for Two BackplanesTest 1 uses a short package, and Test 2 uses a long package. These are reference package traces. The FOM calculation for the backplanes measurements shown in Backplane Measurements are reported for the 26.25-inch channels. This table shows that the Nelco channel would fail test 2 for a basic 26.25-inch NRZ channel. However, the same channel would pass PAM4 due to the mandatory FEC needed when transmitting a PAM4 signal.
Backplane Measurement NRZ NRZ w/ FEC PAM4
Test 1 Test 2 Test 1 Test 2 Test 1 Test 2
Megtron 20" 4.72 4.46 8.44 8.21 6.68 6.86
Megtron 26.25" 4.23 3.66 7.94 7.41 6.67 6.70
Megtron 32.5" 3.31 2.61 (F) 7.06 6.39 6.46 6.39
Megtron 38.75" 1.84 (F) 0.98 (F) 5.68 4.86 5.99 5.80
             
Nelco 20" 4.53 4.02 8.25 7.80 7.34 7.17
Nelco 26.25" 3.02 2.33 (F) 6.81 6.16 6.83 6.58
Nelco 32.5" 1.25 (F) 0.41 (F) 5.13 4.33 6.19 5.87
Nelco 38.75" -1.29 (F) -2.44 (F) 2.66 (F) 1.61 (F) 5.22 4.67
Note: Failing test results are highlighted in bold font, followed by an (F).
Level Two Title