AN 835: PAM4 Signaling Fundamentals

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ID 683852
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. CEI-56G-MR Transmitter 3. CEI-56G-MR-PAM4 Interface Details 4. CEI-56G-MR-PAM4 Receiver 5. PAM4 Link Case Study 6. Medium Reach (MR) PAM4 System Design Study 7. Glossary and Acronyms 8. References 9. Document Revision History for AN 835: PAM4 Signaling Fundamentals
1. Introduction x
1.1. NRZ Fundamentals 1.2. Standards Using PAM4 Coding Scheme 1.3. CEI-56G Interconnect Reaches and Application Distances
1.3. CEI-56G Interconnect Reaches and Application Distances x
1.3.1. VSR (Very Short Reach) Chip-to-Module 1.3.2. MR (Mid-Range Reach) - Chip to Chip Within a PCBA 1.3.3. LR (Long Reach) - Chip to Chip Across a Backplane/Midplane or a Cable
2. CEI-56G-MR Transmitter x
2.1. Naming Conventions 2.2. Eye Height (EH6) and Eye Width (EW6) 2.3. Eye Linearity 2.4. Electrical Characteristics 2.5. PAM4 Jitter Methodology 2.6. TX Pre-Emphasis Method
2.4. Electrical Characteristics x
2.4.1. Transmitter Characteristics 2.4.2. Transmitter Return Loss 2.4.3. Transmitter Linearity (RLM) 2.4.4. Signal-to-Noise-and-Distortion Ratio (SNDR)
3. CEI-56G-MR-PAM4 Interface Details x
3.1. COM Introduction 3.2. Normative Channel Specification COM 3.3. Informative Channel Insertion Loss 3.4. Informative Channel Return Loss
3.1. COM Introduction x
3.1.1. Backplane Measurements
4. CEI-56G-MR-PAM4 Receiver x
4.1. Challenges in Analyzing PAM4 Signals 4.2. PAM4 Receiver Architecture 4.3. Equalization Technique 4.4. CEI-56G-MR-PAM4 Receiver Details
4.2. PAM4 Receiver Architecture x
4.2.1. Analog vs. Digital Receiver 4.2.2. Slicer 4.2.3. Clock and Data Recovery (CDR)
4.4. CEI-56G-MR-PAM4 Receiver Details x
4.4.1. Electrical Characteristics 4.4.2. Receiver Input Return Loss 4.4.3. Receiver Interference Tolerance 4.4.4. Receiver Jitter Tolerance
5. PAM4 Link Case Study x
5.1. OIF_Stressed 5.2. OIF_Compliant
5.1. OIF_Stressed x
5.1.1. Channel Characteristics 5.1.2. OIF_Stressed PAM4 Link Simulation with the Advanced Link Analyzer
5.2. OIF_Compliant x
5.2.1. Channel Characteristics 5.2.2. OIF_Compliant PAM4 Link Simulation with the Advanced Link Analyzer
6. Medium Reach (MR) PAM4 System Design Study x
6.1. System Power 6.2. System Cost 6.3. Board Space 6.4. Conclusion
1. Introduction
2. CEI-56G-MR Transmitter
3. CEI-56G-MR-PAM4 Interface Details
4. CEI-56G-MR-PAM4 Receiver
5. PAM4 Link Case Study
6. Medium Reach (MR) PAM4 System Design Study
7. Glossary and Acronyms
8. References
9. Document Revision History for AN 835: PAM4 Signaling Fundamentals

1.1. NRZ Fundamentals

Ethernet is a family of computer networking technologies that is most widely used in local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN).

Since its commercial introduction in 1980 and first standardization in 1983, Ethernet continues to support increasing demands for a connected world with instant data transmission. Development of 100G Ethernet is currently underway. Achieving greater Ethernet speeds like 200G/400G requires a significant technological advancement. Two coding schemes are possible: Non-Return-to-Zero (NRZ), also known as Pulse-Amplitude Modulation 2-Level (PAM2), and Pulse-Amplitude Modulation 4-Level (PAM4). Because of NRZ’s higher Nyquist frequency which results in higher channel-dependent loss, PAM4 has become a more viable solution.

NRZ is a modulation technique that has two voltage levels to represent logic 0 and logic 1. PAM4 uses four voltage levels to represent four combinations of two bits logic – 11, 10, 01, and 00. Refer to Standards Using PAM4 Coding Scheme for more details about PAM4 naming conventions. Each of the modulation schemes comes with a unique set of advantages and disadvantages.

Figure 1. NRZ (PAM2) and PAM4 CodingCompared with NRZ, PAM4 has the advantages of having half the Nyquist frequency and twice the throughput for the same Baud rate (28 GBaud PAM4 = 56 Gbs) since each voltage level (“symbol”) represents two bits of information. The PAM4 case is not gray encoded.
Figure 2. Power Spectrum Density of NRZ and PAM4At 56 Gbps, PAM4 requires half of the Nyquist frequency as that of NRZ.

PAM4 fNyquist = 56/4 = 14 GHz (Figure 1)

NRZ fNyquist = 56/2 = 28 GHz (Figure 2)

Many benefits are associated with having half the Nyquist frequency. These include: doubling the density of data, achieving higher resolution using the same oversampling rate, and having the same total noise power spread over a wider frequency so that the noise power in bandwidth goes down. However, there are some disadvantages. The PAM4 signal has 1/3 the amplitude of that of a similar NRZ signal. Therefore, the PAM4 signal has a worse Signal-to-Noise Ratio (SNR). Because of the tighter spacing between voltage levels in PAM4 signaling, a PAM4 signal is more susceptible to noise. When all non- linearity effects are added, the SNR loss is approximately 11 dB.

Equation 1. SNR LossThe SNR loss of a PAM4 signal compared to an NRZ signal is ~9.5 dB

A transceiver implementing PAM4 is expected to be more complex and consume higher power than a transceiver supporting NRZ because of the need for more advanced equalization. Because of this complexity, you must determine when using PAM4 is more advantageous than NRZ.

The insertion loss for a Nyquist frequency of 14 GHz on a sample IEEE 802.3 compliant backplane is approximately 33.35 dB.

The same backplane shows an insertion loss of approximately 62 dB for a Nyquist of 28 GHz.

These insertion loss numbers clearly show that it would be much more challenging to equalize the backplane using NRZ than it would when using PAM4.

As shown in the equation for SNR loss, there is a penalty to SNR by using PAM4. However, that penalty is considerably lower than the approximately 11 additional dB that would need to be equalized for the same backplane. Designers can try to minimize insertion loss by using better materials. However, that approach is not possible for legacy systems which are already deployed in the field.

Figure 3. Channel Insertion Loss vs. Nyquist Frequency

Intel® Stratix® 10 family incorporates next-generation transceiver technology to realize today’s large-scale data centers, cloud computing, and wireless applications that require increased bandwidth at lower power and minimum cost per bit. The dual-mode transceivers that are capable of 57.8 Gbps PAM4 and 28.9 Gbps NRZ enable the next-generation high speed interconnects while minimizing insertion loss and crosstalk at terabit data rates. The new standard supports both optical and copper interfaces for chip-to-chip, backplane and direct attach cable applications.

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