HDMI Intel® FPGA IP User Guide

ID 683798
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.2.2.14. VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E)

Table 114.  VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E)
Name Bit(s) Access Description Reset
Reserved 31:16
F0 vertical front porch 15:0 RW Specifies the length of the field 0 vertical front porch (interlaced video only) in lines. 0x0