HDMI Intel® FPGA IP User Guide

ID 683798
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.3.1.1. STATUS (0x01)

Table 125.  STATUS (0x01)
Name Bit Access Description Reset
Reserved 31:9
LTS state 8:6 RO Indicates the current status of the link training state. 0x0
AV muted 5 RO Indicates the current status of the avmute flag. 0x0
Scrambler enabled 4 RO Indicates the current scrambler enable flag. 0x0
TMDS Ratio 3 RO

Indicates the current status of the TMDS bit clock ratio flag.

1'b0 = 1/10

1'b1 = 1/40

0x0
Video lock 2 RO Indicates when the receiver is outputting a stable video signal. 0x0
Alignment lock 1 RO Indicates when the receiver has successfully achieve the data alignment and deskew. 0x0
Cable detect 0 RO Indicates the status of the cable detect signal 0x0