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1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
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3.1.3. Guideline: LVDS Reference Clock Source
The LVDS SERDES IP core accepts two reference clock input sources. Whichever reference clock source you select, you must ensure timing closure.
Reference Clock Input Source | Description | Reference Clock Promotion |
---|---|---|
Dedicated reference clock input within the same I/O bank. | This reference clock input source is the best choice to avoid performance and timing closure issues. | Do not manually promote the reference clock. |
Reference clock input from other I/O banks. | This source must come from another I/O bank and not from other sources such as the hard processor system (HPS), IOPLL IP, or other IPs. This implementation is applicable when you are using LVDS SERDES TX, RX DPA-FIFO, and RX soft-CDR functional mode. 2 | You must manually promote the reference clock. |
To manually promote the reference clock, include this statement in your Quartus® Prime settings file (.qsf):
set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of top-level reference clock input port>
Related Information
2 Promoting reference clock input from other I/O bank through global clock network is not supported when you are using LVDS SERDES RX in non-DPA mode.