Visible to Intel only — GUID: sam1412833665780
Ixiasoft
Visible to Intel only — GUID: sam1412833665780
Ixiasoft
4.3.2. FPGA Timing Analysis
Clock | Clock Name |
---|---|
Core clock | <pll_instance_name>_*_outclk[*] |
LVDS SERDES fast clock | <pll_instance_name>_*_lvds_clk[*] |
Clock | Clock Name |
---|---|
Core clock | <lvds_instance_name>_core_ck_name_<channel_num> |
DPA fast clock | <lvds_instance_name>_dpa_ck_name_<channel_num> |
To ensure proper timing analysis, instead of multicycle constraints, the IP creates clock settings at rx_out in the following format:
- For rising edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>
- For falling edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>_neg
With these proper clock settings, the Timing Analyzer can correctly analyze the timing of the LVDS SERDES–core interface transfer and within the core transfer.