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1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
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2.5.2.2. DPA Mode
The DPA block chooses the best possible clock (dpa_fast_clock) from the eight fast clocks that the I/O PLL sent. This serial dpa_fast_clock clock is used for writing the serial data into the synchronizer. A serial fast_clock clock is used for reading the serial data from the synchronizer. The same fast_clock clock is used in data realignment and deserializer blocks.
Figure 14. Receiver Datapath in DPA Mode This figure shows the DPA mode datapath. In the figure, all the receiver hardware blocks are active.
Note: In DPA mode, you must place all receiver channels of an LVDS instance in one I/O bank. Because each I/O bank has a maximum of 24 LVDS I/O buffer pairs, each LVDS instance can support a maximum of 24 DPA channels.