Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4.2.5. GPIO Intel® FPGA IP Timing

The performance of the GPIO IP depends on the I/O constraints and clock phases. To validate the timing for your GPIO configuration, Intel recommends that you use the Timing Analyzer.