Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

Download PDF
ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview 2. Intel® Agilex™ I/O Features and Usage 3. Intel® Agilex™ I/O Termination 4. Intel® Agilex™ High-Speed SERDES I/O Architecture 5. I/O and LVDS SERDES Design Guidelines 6. Troubleshooting Guidelines 7. Documentation Related to the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide 8. Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives 9. Document Revision History for the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview x
1.1. Intel® Agilex™ I/O and Differential I/O Buffers 1.2. Package Selection and I/O Vertical Migration Support 1.3. I/O Banks
1.3. I/O Banks x
1.3.1. I/O Buffer and Registers in Intel® Agilex™ Devices
2. Intel® Agilex™ I/O Features and Usage x
2.1. GPIO Features 2.2. Programmable I/O Element (IOE) Features in Intel® Agilex™ Devices 2.3. I/O Standards and Features for Intel® Agilex™ Configuration Pins 2.4. I/O Implementation Guide
2.1. GPIO Features x
2.1.1. Supported I/O Standards 2.1.2. Intel® Agilex™ I/O Buffer Behavior
2.2. Programmable I/O Element (IOE) Features in Intel® Agilex™ Devices x
2.2.1. Programmable Output Slew Rate Control 2.2.2. Programmable IOE Delay 2.2.3. Programmable Open-Drain Output 2.2.4. Programmable Bus-Hold 2.2.5. Programmable Pull-Up Resistor 2.2.6. Programmable Pre-emphasis 2.2.7. Programmable De-emphasis 2.2.8. Programmable Differential Output Voltage 2.2.9. Schmitt Trigger Input Buffer
2.4. I/O Implementation Guide x
2.4.1. Configuring I/O Assignments in Intel® Quartus® Prime Software 2.4.2. Using GPIO Intel FPGA IP for I/O Implementation
2.4.1. Configuring I/O Assignments in Intel® Quartus® Prime Software x
2.4.1.1. Configuring I/O Assignments Using Assignment Editor 2.4.1.2. Configuring I/O Standards Using Pin Planner
2.4.2. Using GPIO Intel FPGA IP for I/O Implementation x
2.4.2.1. Release Information 2.4.2.2. GPIO Intel FPGA IP Quick Start Guide 2.4.2.3. GPIO Intel® FPGA IP Architecture 2.4.2.4. Verifying Resource Utilization and Design Performance 2.4.2.5. GPIO Intel® FPGA IP Timing 2.4.2.6. GPIO Intel® FPGA IP Design Examples
2.4.2.2. GPIO Intel FPGA IP Quick Start Guide x
2.4.2.2.1. Generating the GPIO Intel FPGA IP ( Intel® Quartus® Prime Pro Edition) 2.4.2.2.2. GPIO Intel® FPGA IP Parameter Settings 2.4.2.2.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.4.2.2.4. GPIO Intel® FPGA IP Interface Signals
2.4.2.3. GPIO Intel® FPGA IP Architecture x
2.4.2.3.1. GPIO Intel® FPGA IP Data Paths 2.4.2.3.2. Register Packing
2.4.2.5. GPIO Intel® FPGA IP Timing x
2.4.2.5.1. Timing Components 2.4.2.5.2. Delay Elements 2.4.2.5.3. Full-Rate or Half-Rate DDIO Output Register 2.4.2.5.4. Timing Analysis 2.4.2.5.5. Timing Closure Guidelines
2.4.2.6. GPIO Intel® FPGA IP Design Examples x
2.4.2.6.1. GPIO Intel FPGA IP Synthesizable Intel® Quartus® Prime Design Example 2.4.2.6.2. GPIO Intel FPGA IP Simulation Design Example
3. Intel® Agilex™ I/O Termination x
3.1. Single-Ended I/O Termination in Intel® Agilex™ Devices 3.2. True Differential Signaling I/O Termination
3.1. Single-Ended I/O Termination in Intel® Agilex™ Devices x
3.1.1. Single-Ended I/O Standard OCT Termination 3.1.2. OCT Calibration Block 3.1.3. Single-ended I/O Standards External Termination 3.1.4. Single-ended I/O Termination Implementation Guide
3.1.1. Single-Ended I/O Standard OCT Termination x
3.1.1.1. RS OCT 3.1.1.2. RT OCT 3.1.1.3. Dynamic OCT
3.1.4. Single-ended I/O Termination Implementation Guide x
3.1.4.1. Configuring OCT Using Assignment Editor 3.1.4.2. Using OCT Intel FPGA IP for I/O Termination Implementation
3.1.4.2. Using OCT Intel FPGA IP for I/O Termination Implementation x
3.1.4.2.1. Release Information 3.1.4.2.2. OCT Intel® FPGA IP Quick Start Guide 3.1.4.2.3. OCT Intel® FPGA IP Architecture 3.1.4.2.4. OCT Intel® FPGA IP Design Example
3.2. True Differential Signaling I/O Termination x
3.2.1. External I/O Termination 3.2.2. True Differential Signaling I/O Standard OCT Termination
3.2.2. True Differential Signaling I/O Standard OCT Termination x
3.2.2.1. Configuring Differential Input RD OCT Using Assignment Editor 3.2.2.2. Differential Input RD OCT Restrictions and Guidelines
4. Intel® Agilex™ High-Speed SERDES I/O Architecture x
4.1. Intel® Agilex™ High-Speed SERDES I/O Overview 4.2. Using LVDS SERDES Intel FPGA IP for High-Speed LVDS I/O Implementation 4.3. Intel® Agilex™ LVDS SERDES Transmitter 4.4. Intel® Agilex™ LVDS SERDES Receiver 4.5. Intel® Agilex™ LVDS Interface with External PLL Mode 4.6. LVDS SERDES IP Initialization and Reset 4.7. Intel® Agilex™ LVDS SERDES Source-Synchronous Timing Budget 4.8. LVDS SERDES IP Timing 4.9. LVDS SERDES IP Design Examples
4.1. Intel® Agilex™ High-Speed SERDES I/O Overview x
4.1.1. High-Speed SERDES Architecture 4.1.2. Intel® Agilex™ GPIO Banks, SERDES, and DPA Locations
4.2. Using LVDS SERDES Intel FPGA IP for High-Speed LVDS I/O Implementation x
4.2.1. Release Information 4.2.2. LVDS SERDES Intel FPGA IP Quick Start Guide
4.2.2. LVDS SERDES Intel FPGA IP Quick Start Guide x
4.2.2.1. Generating the LVDS SERDES Intel FPGA IP ( Intel® Quartus® Prime Pro Edition) 4.2.2.2. LVDS SERDES Intel® FPGA IP Parameter Settings 4.2.2.3. IP Generation Output ( Intel® Quartus® Prime Pro Edition) 4.2.2.4. LVDS SERDES IP Signals
4.2.2.2. LVDS SERDES Intel® FPGA IP Parameter Settings x
4.2.2.2.1. LVDS SERDES IP General Settings 4.2.2.2.2. LVDS SERDES IP PLL Settings 4.2.2.2.3. LVDS SERDES IP Receiver Settings 4.2.2.2.4. LVDS SERDES IP Transmitter Settings 4.2.2.2.5. LVDS SERDES IP Clock Resource Summary
4.3. Intel® Agilex™ LVDS SERDES Transmitter x
4.3.1. LVDS SERDES Transmitter Blocks 4.3.2. Serializer Bypass for DDR and SDR Operations 4.3.3. Serializer 4.3.4. Differential I/O Bit Position 4.3.5. Clocking Differential Transmitters
4.3.5. Clocking Differential Transmitters x
4.3.5.1. Setting the Transmitter Output Clock Parameters
4.4. Intel® Agilex™ LVDS SERDES Receiver x
4.4.1. LVDS SERDES Receiver Blocks 4.4.2. Clocking LVDS SERDES Receivers 4.4.3. LVDS SERDES Receiver Modes
4.4.1. LVDS SERDES Receiver Blocks x
4.4.1.1. Receiver Blocks in Intel® Agilex™ Devices
4.4.1.1. Receiver Blocks in Intel® Agilex™ Devices x
4.4.1.1.1. DPA Block 4.4.1.1.2. Synchronizer (DPA FIFO) 4.4.1.1.3. Data Realignment Block (Bit Slip) 4.4.1.1.4. Deserializer
4.4.2. Clocking LVDS SERDES Receivers x
4.4.2.1. Receiver Input Clock Parameters Setup
4.4.3. LVDS SERDES Receiver Modes x
4.4.3.1. Non-DPA Mode 4.4.3.2. DPA Mode 4.4.3.3. Soft-CDR Mode
4.5. Intel® Agilex™ LVDS Interface with External PLL Mode x
4.5.1. IOPLL IP Signal Interface with LVDS SERDES IP 4.5.2. IOPLL Parameter Values for External PLL Mode 4.5.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
4.6. LVDS SERDES IP Initialization and Reset x
4.6.1. Initializing the LVDS SERDES IP in Non-DPA Mode 4.6.2. Initializing the LVDS SERDES IP in DPA Mode 4.6.3. Resetting the DPA 4.6.4. Word Boundaries Alignment
4.6.4. Word Boundaries Alignment x
4.6.4.1. Aligning Word Boundaries
4.7. Intel® Agilex™ LVDS SERDES Source-Synchronous Timing Budget x
4.7.1. Transmitter Channel-to-Channel Skew 4.7.2. Receiver Skew Margin
4.8. LVDS SERDES IP Timing x
4.8.1. I/O Timing Analysis 4.8.2. FPGA Timing Analysis 4.8.3. Timing Analysis for the External PLL Mode
4.8.1. I/O Timing Analysis x
4.8.1.1. Obtaining RSKM Report 4.8.1.2. Obtaining TCCS Report
4.9. LVDS SERDES IP Design Examples x
4.9.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples 4.9.2. LVDS SERDES IP Simulation Design Example 4.9.3. Combined LVDS SERDES IP Transmitter and Receiver Design Example 4.9.4. LVDS SERDES IP Dynamic Phase Shift Design Example
5. I/O and LVDS SERDES Design Guidelines x
5.1. Intel® Agilex™ I/O Design Guidelines 5.2. Intel® Agilex™ LVDS SERDES Design Guidelines
5.1. Intel® Agilex™ I/O Design Guidelines x
5.1.1. VREF Sources and VREF Pins 5.1.2. I/O Standards Implementation based on VCCIO_PIO Voltages 5.1.3. OCT Calibration Block Requirement 5.1.4. Placement Requirements 5.1.5. Simultaneous Switching Noise (SSN) 5.1.6. Special Pins Requirement 5.1.7. External Memory Interface Pin Placement Requirements 5.1.8. HPS Shared I/O Requirements 5.1.9. Clocking Requirements 5.1.10. SDM Shared I/O Requirements 5.1.11. Configuration Pins 5.1.12. Unused Pins 5.1.13. Voltage Setting for Unused I/O Banks 5.1.14. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing 5.1.15. Drive Strength Requirement for GPIO Input Pins 5.1.16. Maximum DC Current Restrictions 5.1.17. 1.2 V I/O Interface Voltage Level Compatibility 5.1.18. GPIO Pins for Avalon-ST Configuration Scheme 5.1.19. Maximum True Differential Signaling RX Pairs Per I/O Lane 5.1.20. I/O Simulation
5.1.20. I/O Simulation x
5.1.20.1. HSPICE* Models 5.1.20.2. Net Length Reports
5.2. Intel® Agilex™ LVDS SERDES Design Guidelines x
5.2.1. Use PLLs in Integer PLL Mode for LVDS 5.2.2. Use High-Speed Clock from PLL to Clock SERDES Only 5.2.3. Pin Placement for Differential Channels 5.2.4. SERDES Pin Pairs for Soft-CDR Mode 5.2.5. Placing LVDS Transmitters and Receivers in the Same I/O Bank
5.2.5. Placing LVDS Transmitters and Receivers in the Same I/O Bank x
5.2.5.1. Using an External PLL
1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview
2. Intel® Agilex™ I/O Features and Usage
3. Intel® Agilex™ I/O Termination
4. Intel® Agilex™ High-Speed SERDES I/O Architecture
5. I/O and LVDS SERDES Design Guidelines
6. Troubleshooting Guidelines
7. Documentation Related to the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
8. Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives
9. Document Revision History for the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

5.1.14. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing

Intel® Agilex™ devices do not support hot-socketing and require a specific power sequence. Design your power supply solution to properly control the complete power sequence.

Adhere to the following guidelines to prevent unnecessary current draw on the I/O pins located in the GPIO, HPS, and SDM banks. These guidelines are applicable for unpowered, power up to POR, POR delay, POR delay to configuration, configuration, initialization, user mode, and power down device states.

  • The I/O pins in these banks can be in one the following states:
    • GPIO banks—tri-stated, driven to ground, or driven to the VCCIO_PIO level.
    • HPS banks—tri-stated, driven to ground, or driven to the VCCIO_HPS level.
    • SDM banks—tri-stated, driven to ground, or driven to the VCCIO_SDM level.
  • While the Intel® Agilex™ device is powering up or down:
    • The input signals of an I/O pin at all times must not exceed the I/O buffer power supply rail of the bank where the I/O pin resides.
    • If you use a pin in a GPIO bank with 1.5 V VCCIO_PIO, the pin voltage must not exceed the VCCIO_PIO rail or 1.2 V, whichever is lower.
  • While the Intel® Agilex™ device is powering up, powering down, or not turned on, the GPIO, SDM, and HPS pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per I/O bank.
  • After the Intel® Agilex™ device fully powers up, the voltage levels for the GPIO, SDM, and HPS pins must not exceed the DC input voltage (VI) value.
Table 80.  Guideline Examples
Condition Guideline
The VCCIO_SDM pin ramps up and at period X, the VCCIO_SDM voltage is 0.9 V. At period X, keep the signals driven by the device connected to the SDM I/O pin at a voltage of 0.9 V or lower.
The VCCIO_PIO pin ramps up and at period X, the VCCIO_PIO voltage is 1.1 V. At period X, keep the signals driven by the device connected to the GPIO I/O pin at a voltage of 1.1 V or lower.
The 1.5 V VCCIO_PIO pin ramps up and the voltage continues to rise pass the 1.2 V level. Keep the GPIO I/O pin voltage at 1.2 V or lower until the Intel® Agilex™ device fully powers up.
Related Information
Level Two Title