Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

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ID 683780
Date 10/29/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview 2. Intel® Agilex™ I/O Features and Usage 3. Intel® Agilex™ I/O Termination 4. Intel® Agilex™ High-Speed SERDES I/O Architecture 5. I/O and LVDS SERDES Design Guidelines 6. Troubleshooting Guidelines 7. Documentation Related to the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide 8. Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives 9. Document Revision History for the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview x
1.1. Intel® Agilex™ I/O and Differential I/O Buffers 1.2. Package Selection and I/O Vertical Migration Support 1.3. I/O Banks
1.3. I/O Banks x
1.3.1. I/O Buffer and Registers in Intel® Agilex™ Devices
2. Intel® Agilex™ I/O Features and Usage x
2.1. GPIO Features 2.2. Programmable I/O Element (IOE) Features in Intel® Agilex™ Devices 2.3. I/O Standards and Features for Intel® Agilex™ Configuration Pins 2.4. I/O Implementation Guide
2.1. GPIO Features x
2.1.1. Supported I/O Standards 2.1.2. Intel® Agilex™ I/O Buffer Behavior
2.2. Programmable I/O Element (IOE) Features in Intel® Agilex™ Devices x
2.2.1. Programmable Output Slew Rate Control 2.2.2. Programmable IOE Delay 2.2.3. Programmable Open-Drain Output 2.2.4. Programmable Bus-Hold 2.2.5. Programmable Pull-Up Resistor 2.2.6. Programmable Pre-emphasis 2.2.7. Programmable De-emphasis 2.2.8. Programmable Differential Output Voltage 2.2.9. Schmitt Trigger Input Buffer
2.4. I/O Implementation Guide x
2.4.1. Configuring I/O Assignments in Intel® Quartus® Prime Software 2.4.2. Using GPIO Intel FPGA IP for I/O Implementation
2.4.1. Configuring I/O Assignments in Intel® Quartus® Prime Software x
2.4.1.1. Configuring I/O Assignments Using Assignment Editor 2.4.1.2. Configuring I/O Standards Using Pin Planner
2.4.2. Using GPIO Intel FPGA IP for I/O Implementation x
2.4.2.1. Release Information 2.4.2.2. GPIO Intel FPGA IP Quick Start Guide 2.4.2.3. GPIO Intel® FPGA IP Architecture 2.4.2.4. Verifying Resource Utilization and Design Performance 2.4.2.5. GPIO Intel® FPGA IP Timing 2.4.2.6. GPIO Intel® FPGA IP Design Examples
2.4.2.2. GPIO Intel FPGA IP Quick Start Guide x
2.4.2.2.1. Generating the GPIO Intel FPGA IP ( Intel® Quartus® Prime Pro Edition) 2.4.2.2.2. GPIO Intel® FPGA IP Parameter Settings 2.4.2.2.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.4.2.2.4. GPIO Intel® FPGA IP Interface Signals
2.4.2.3. GPIO Intel® FPGA IP Architecture x
2.4.2.3.1. GPIO Intel® FPGA IP Data Paths 2.4.2.3.2. Register Packing
2.4.2.5. GPIO Intel® FPGA IP Timing x
2.4.2.5.1. Timing Components 2.4.2.5.2. Delay Elements 2.4.2.5.3. Full-Rate or Half-Rate DDIO Output Register 2.4.2.5.4. Timing Analysis 2.4.2.5.5. Timing Closure Guidelines
2.4.2.6. GPIO Intel® FPGA IP Design Examples x
2.4.2.6.1. GPIO Intel FPGA IP Synthesizable Intel® Quartus® Prime Design Example 2.4.2.6.2. GPIO Intel FPGA IP Simulation Design Example
3. Intel® Agilex™ I/O Termination x
3.1. Single-Ended I/O Termination in Intel® Agilex™ Devices 3.2. True Differential Signaling I/O Termination
3.1. Single-Ended I/O Termination in Intel® Agilex™ Devices x
3.1.1. Single-Ended I/O Standard OCT Termination 3.1.2. OCT Calibration Block 3.1.3. Single-ended I/O Standards External Termination 3.1.4. Single-ended I/O Termination Implementation Guide
3.1.1. Single-Ended I/O Standard OCT Termination x
3.1.1.1. RS OCT 3.1.1.2. RT OCT 3.1.1.3. Dynamic OCT
3.1.4. Single-ended I/O Termination Implementation Guide x
3.1.4.1. Configuring OCT Using Assignment Editor 3.1.4.2. Using OCT Intel FPGA IP for I/O Termination Implementation
3.1.4.2. Using OCT Intel FPGA IP for I/O Termination Implementation x
3.1.4.2.1. Release Information 3.1.4.2.2. OCT Intel® FPGA IP Quick Start Guide 3.1.4.2.3. OCT Intel® FPGA IP Architecture 3.1.4.2.4. OCT Intel® FPGA IP Design Example
3.2. True Differential Signaling I/O Termination x
3.2.1. External I/O Termination 3.2.2. True Differential Signaling I/O Standard OCT Termination
3.2.2. True Differential Signaling I/O Standard OCT Termination x
3.2.2.1. Configuring Differential Input RD OCT Using Assignment Editor 3.2.2.2. Differential Input RD OCT Restrictions and Guidelines
4. Intel® Agilex™ High-Speed SERDES I/O Architecture x
4.1. Intel® Agilex™ High-Speed SERDES I/O Overview 4.2. Using LVDS SERDES Intel FPGA IP for High-Speed LVDS I/O Implementation 4.3. Intel® Agilex™ LVDS SERDES Transmitter 4.4. Intel® Agilex™ LVDS SERDES Receiver 4.5. Intel® Agilex™ LVDS Interface with External PLL Mode 4.6. LVDS SERDES IP Initialization and Reset 4.7. Intel® Agilex™ LVDS SERDES Source-Synchronous Timing Budget 4.8. LVDS SERDES IP Timing 4.9. LVDS SERDES IP Design Examples
4.1. Intel® Agilex™ High-Speed SERDES I/O Overview x
4.1.1. High-Speed SERDES Architecture 4.1.2. Intel® Agilex™ GPIO Banks, SERDES, and DPA Locations
4.2. Using LVDS SERDES Intel FPGA IP for High-Speed LVDS I/O Implementation x
4.2.1. Release Information 4.2.2. LVDS SERDES Intel FPGA IP Quick Start Guide
4.2.2. LVDS SERDES Intel FPGA IP Quick Start Guide x
4.2.2.1. Generating the LVDS SERDES Intel FPGA IP ( Intel® Quartus® Prime Pro Edition) 4.2.2.2. LVDS SERDES Intel® FPGA IP Parameter Settings 4.2.2.3. IP Generation Output ( Intel® Quartus® Prime Pro Edition) 4.2.2.4. LVDS SERDES IP Signals
4.2.2.2. LVDS SERDES Intel® FPGA IP Parameter Settings x
4.2.2.2.1. LVDS SERDES IP General Settings 4.2.2.2.2. LVDS SERDES IP PLL Settings 4.2.2.2.3. LVDS SERDES IP Receiver Settings 4.2.2.2.4. LVDS SERDES IP Transmitter Settings 4.2.2.2.5. LVDS SERDES IP Clock Resource Summary
4.3. Intel® Agilex™ LVDS SERDES Transmitter x
4.3.1. LVDS SERDES Transmitter Blocks 4.3.2. Serializer Bypass for DDR and SDR Operations 4.3.3. Serializer 4.3.4. Differential I/O Bit Position 4.3.5. Clocking Differential Transmitters
4.3.5. Clocking Differential Transmitters x
4.3.5.1. Setting the Transmitter Output Clock Parameters
4.4. Intel® Agilex™ LVDS SERDES Receiver x
4.4.1. LVDS SERDES Receiver Blocks 4.4.2. Clocking LVDS SERDES Receivers 4.4.3. LVDS SERDES Receiver Modes
4.4.1. LVDS SERDES Receiver Blocks x
4.4.1.1. Receiver Blocks in Intel® Agilex™ Devices
4.4.1.1. Receiver Blocks in Intel® Agilex™ Devices x
4.4.1.1.1. DPA Block 4.4.1.1.2. Synchronizer (DPA FIFO) 4.4.1.1.3. Data Realignment Block (Bit Slip) 4.4.1.1.4. Deserializer
4.4.2. Clocking LVDS SERDES Receivers x
4.4.2.1. Receiver Input Clock Parameters Setup
4.4.3. LVDS SERDES Receiver Modes x
4.4.3.1. Non-DPA Mode 4.4.3.2. DPA Mode 4.4.3.3. Soft-CDR Mode
4.5. Intel® Agilex™ LVDS Interface with External PLL Mode x
4.5.1. IOPLL IP Signal Interface with LVDS SERDES IP 4.5.2. IOPLL Parameter Values for External PLL Mode 4.5.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
4.6. LVDS SERDES IP Initialization and Reset x
4.6.1. Initializing the LVDS SERDES IP in Non-DPA Mode 4.6.2. Initializing the LVDS SERDES IP in DPA Mode 4.6.3. Resetting the DPA 4.6.4. Word Boundaries Alignment
4.6.4. Word Boundaries Alignment x
4.6.4.1. Aligning Word Boundaries
4.7. Intel® Agilex™ LVDS SERDES Source-Synchronous Timing Budget x
4.7.1. Transmitter Channel-to-Channel Skew 4.7.2. Receiver Skew Margin
4.8. LVDS SERDES IP Timing x
4.8.1. I/O Timing Analysis 4.8.2. FPGA Timing Analysis 4.8.3. Timing Analysis for the External PLL Mode
4.8.1. I/O Timing Analysis x
4.8.1.1. Obtaining RSKM Report 4.8.1.2. Obtaining TCCS Report
4.9. LVDS SERDES IP Design Examples x
4.9.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples 4.9.2. LVDS SERDES IP Simulation Design Example 4.9.3. Combined LVDS SERDES IP Transmitter and Receiver Design Example 4.9.4. LVDS SERDES IP Dynamic Phase Shift Design Example
5. I/O and LVDS SERDES Design Guidelines x
5.1. Intel® Agilex™ I/O Design Guidelines 5.2. Intel® Agilex™ LVDS SERDES Design Guidelines
5.1. Intel® Agilex™ I/O Design Guidelines x
5.1.1. VREF Sources and VREF Pins 5.1.2. I/O Standards Implementation based on VCCIO_PIO Voltages 5.1.3. OCT Calibration Block Requirement 5.1.4. Placement Requirements 5.1.5. Simultaneous Switching Noise (SSN) 5.1.6. Special Pins Requirement 5.1.7. External Memory Interface Pin Placement Requirements 5.1.8. HPS Shared I/O Requirements 5.1.9. Clocking Requirements 5.1.10. SDM Shared I/O Requirements 5.1.11. Configuration Pins 5.1.12. Unused Pins 5.1.13. Voltage Setting for Unused I/O Banks 5.1.14. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing 5.1.15. Drive Strength Requirement for GPIO Input Pins 5.1.16. Maximum DC Current Restrictions 5.1.17. 1.2 V I/O Interface Voltage Level Compatibility 5.1.18. GPIO Pins for Avalon-ST Configuration Scheme 5.1.19. Maximum True Differential Signaling RX Pairs Per I/O Lane 5.1.20. I/O Simulation
5.1.20. I/O Simulation x
5.1.20.1. HSPICE* Models 5.1.20.2. Net Length Reports
5.2. Intel® Agilex™ LVDS SERDES Design Guidelines x
5.2.1. Use PLLs in Integer PLL Mode for LVDS 5.2.2. Use High-Speed Clock from PLL to Clock SERDES Only 5.2.3. Pin Placement for Differential Channels 5.2.4. SERDES Pin Pairs for Soft-CDR Mode 5.2.5. Placing LVDS Transmitters and Receivers in the Same I/O Bank
5.2.5. Placing LVDS Transmitters and Receivers in the Same I/O Bank x
5.2.5.1. Using an External PLL
1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview
2. Intel® Agilex™ I/O Features and Usage
3. Intel® Agilex™ I/O Termination
4. Intel® Agilex™ High-Speed SERDES I/O Architecture
5. I/O and LVDS SERDES Design Guidelines
6. Troubleshooting Guidelines
7. Documentation Related to the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
8. Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives
9. Document Revision History for the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

9. Document Revision History for the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.10.29 21.3
  • Updated the topic about the I/O buffer behavior to add more details on the power up, power down, and turned off conditions.
  • Updated the guidelines for I/O pins in GPIO, HPS, and SDM banks during power sequencing.
  • Added a section listing the I/O standards and features for configuration pins in different configuration schemes.
  • Removed the table listing the configuration pin I/O standards and features.
2021.10.04 21.3
  • Updated the package selection and I/O vertical migration information.
  • Updated the topic about programmable de-emphasis:
    • The de-emphasis effect now affects signals at 1 UI or 0.5 UI depending on the interface clock frequency.
    • Restructured the content for easier reference.
  • Updated the GPIO IP version to 21.0.0.
  • Removed NCSim support.
2021.07.15 21.2 Updated the diagram that shows the simplified view of the single-ended GPIO input path to update dout[0] to dout[3] and dout[3] to dout[0].
2021.04.05 21.1
  • Updated the vertical migration table:
    • Removed the AGF 004 product line.
    • Removed the F1149A, R1615A, R2013A, R2470A, R3179C, R2581A, R3179B, and R3179A packages.
    • Added R1546A, R2340A, R3184C, F2581A, R3184B, and R3184A packages.
  • Removed H-tile and 3 V I/O support.
  • Removed the Intel® Agilex™ AGF 014 FPGA.
  • Updated default settings for the POD-12 and Differential POD-12 I/O standards from "High" to "Off".
  • Added a topic about the Schmitt Trigger input buffer feature.
  • Added assignment settings for the Schmitt Trigger input buffer.
  • Added support for assigning 0 V, 1.2 V, or 1.5 V to the VCCIO_PIO pin in unused I/O banks.
  • Updated the figures showing the I/O bank structure to improve clarity and to remove 3 V I/O.
  • Updated the IP version for the GPIO and LVDS SERDES IPs to 20.0.0.
2020.09.28 20.3
  • Added 3 V H-tile I/O information in the following topics:
    • General-purpose I/O and LVDS SERDES Overview.
    • Intel® Agilex™ I/O and Differential I/O Buffers.
    • I/O Banks.
    • Supported I/O Standards.
    • Programmable I/O Element (IOE) Features in Intel® Agilex™ Devices.
    • Single-Ended I/O Standard OCT Termination.
    • RS OCT.
    • Single-ended I/O Standards External Termination.
    • Input Path.
    • GPIO Intel FPGA IP Architecture.
  • Updated the voltage level of a pin signal during power down in the I/O Buffer Behavior.
  • Updated the Supported Usage Modes with Number of IP Instances in an I/O Sub-bank table to clarified the maximum number of transmitter and receiver channels per IP instance.
  • Updated lvds_clk and ext_lvds_clk signals width in the following tables:
    • Example: Generating Output Clocks Using an IOPLL IP (Receiver in Non-DPA Mode).
    • Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode).
    • Example: Generating Output Clocks Using a Shared IOPLL IP for Transmitter and Receiver Channels (Receiver in DPA or Soft-CDR Mode).
  • Removed information about transmitter spanning across multiple I/O banks feature in the following topics:
    • IOPLL Parameter Values for External PLL Mode.
    • Intel® Agilex™ LVDS Interface with External PLL Mode.
  • Updated the IOPLL IP settings in the Signal Interface between IOPLL and LVDS SERDES IPs table.
  • Updated the Soft-CDR LVDS Receiver Interface with the IOPLL IP (with LVDS transmitter in the same sub-bank) figure.
  • Added the following guideline topics in the I/O Design Guidelines chapter:
    • Voltage Setting for Unused I/O Banks.
    • Drive Strength Requirement for GPIO Input Pins.
    • Observe Device Absolute Maximum Rating for 3.0 V Interfacing.
    • Use Only One Voltage for All 3 V I/O Banks.
    • Maximum True Differential Signaling RX Pairs Per I/O Lane.
    • Do Not Drive 3 V I/O Pins During Power Sequencing.
  • Updated LVDS SERDES Intel FPGA IP version to 19.5.0 with the following change:
    • Improved the power usage of the IP.
    • Removed the Duplex Feature parameter in the General Settings Tab table.
    • Updated the condition for FPGA/PLL speed grade in the PLL Settings Tab table.
  • Added short descriptions for General-purpose I/O Debug Guidelines and High-speed SERDES I/O Debug Guidelines tables.
2020.06.22 20.2
  • Changed R2560A name to R2581A in the Migration Capability Across Intel® Agilex™ Product Lines—Preliminary image.
  • Clarified that programmable de-emphasis feature is only available when using Fast slew rate setting in the Programmable IOE Feature Settings for Intel® Agilex™ GPIO Bank table and Programmable De-Emphasis section.
  • Added new GPIO Pins for Avalon-ST Configuration Scheme guideline topic.
  • Added the Troubleshooting Guidelines topic.
  • Added the following KDB links to the Transmitter Channel-to-Channel Skew and Receiver Skew Margin topics:
    • Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?
    • Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?
  • Added the release notes links to the GPIO Intel FPGA IP Release Information, OCT Intel FPGA IP Release Information, and LVDS SERDES Intel FPGA IP Release Information topics.
2020.04.13 20.1
  • Updated the Programmable IOE Feature Settings for Intel® Agilex™ GPIO Bank table with default slew rate settings for GPIO and EMIF implementations.
  • Updated the Programmable Output Slew Rate Control topic to specify different slew rate settings per design implementation.
  • Removed recommendation to use HSPICE simulation to verify output voltages in th e Programmable Open-Drain Output topic.
  • Updated guidelines in the External I/O Termination topic.
  • Added the AC-Coupled External Termination for 1.2 V VCCIO_PIO figure in the External I/O Termination.
  • Added the Simulation Models Descriptions table in the I/O Simulation topic.
  • Updated OCT Intel FPGA IP and GPIO Intel FPGA IP connections for user mode calibration in the User Mode OCT topic.
  • Added RZQ_GROUP QSF assignment description in the QSF Assignments table.
  • Added OCT block and primitive I/O buffer connection figure in the QSF Assignments topic.
  • Renamed the Guidelines for GPIO Pins During Power Sequencing section to Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing and updated the guidelines for GPIO, HPS, and SDM I/O pins in the section.
  • Updated information about LVDS SERDES Intel FPGA IP version 19.4.0:
    • Updated pll_areset signal connections in Non-DPA or DPA LVDS Receiver Interface with the IP (with LVDS transmitter in the same sub-bank), Soft-CDR LVDS Receiver Interface with the IP (with LVDS transmitter in the same sub-bank), and LVDS Transmitter Interface with the IP figures.
    • Added description for ext_pll_locked signal in the External PLL Signals for LVDS SERDES IP and the Signal Interface between IOPLL and LVDS SERDES IPs tables.
    • Added a note about the delay between the ext_pll_locked signal and the pll_locked signal assertions in the Initializing the LVDS SERDES IP in DPA Mode and the Initializing the LVDS SERDES IP in Non-DPA Mode topics.
2019.12.16 19.4
  • Updated information for GPIO Intel FPGA IP version 19.3.0:
    • Changed seriesterminationcontrol and parallelterminationcontrol signals to terminationcontrol signal.
  • Updated description on calibration block for mix I/O standards in the OCT Calibration Block topic.
  • Added information about LVDS SERDES Intel FPGA IP version 19.3.0.
  • Added Example of x4 DQ Groups with Shared OE, Reset, and Clock Enable Signals in Pinout Files figure in the Placement Requirements topic.
  • Added Simultaneous Switching Noise and Clocking Requirements topics in the I/O Design Guidelines chapter.
  • Added Placing LVDS Transmitters and Receivers in the Same I/O Bank and Using an External PLL topics in the LVDS SERDES Design Guidelines chapter.
  • Added information to generate design example for OCT Intel FPGA IP version 19.3.0.
  • Added Net Length Reports topic.
2019.09.30 19.3
  • Changed differential signaling naming from 1.5 V True Differential Signaling to True Differential Signaling.
  • Added Input and Output columns for VCCIO_PIO voltage in the Intel® Agilex™ GPIO Bank Supported I/O Standards table.
  • Added Intel® Quartus® Prime assignment names for each I/O standards.
  • Added the following topics:
    • I/O Buffer and Registers in Intel® Agilex™ Devices
    • Configuring I/O Assignments in Intel® Quartus® Prime Software
    • Configuring I/O Assignments Using Assignment Editor
    • Configuring I/O Standards Using Pin Planner
    • Configuring OCT Using Assignment Editor
    • Configuring Differential Input RD OCT Using Assignment Editor
  • Restructured the Intel® Agilex™ I/O Termination chapter.
  • Updated default RS OCT calibration values in the Selectable I/O Standards for RS OCT table.
  • Added explanation on the number of RS and RT OCT settings can a OCT calibration block supports for all I/O standards in OCT Calibration Block topic.
  • Restructured the I/O and LVDS SERDES Design Guidelines chapter.
  • Added the following diagrams in the Programmable De-Emphasis section:
    • Signal Attenuation for De-emphasis Off for SSTL and HSTL I/O Standards
    • Signal Attenuation for Constant Impedance De-emphasis for SSTL and HSTL I/O Standards
    • Signal Attenuation for Low Power De-emphasis for SSTL and HSTL I/O Standards
    • Signal Attenuation for De-emphasis Off for POD12 I/O Standard
    • Signal Attenuation for Low Power De-emphasis for POD12 I/O Standard
  • Removed maximum DC current restrictions for Intel® Agilex™ devices in the Maximum DC Current Restrictions topic.
  • Added the OCT Calibration Block Requirement topic in Intel® Agilex™ I/O Design Guidelines.
  • Added new restrictions about using AVSTx16 or AVSTx32 configuration scheme in SDM Shared I/O Requirements topic.
  • Changed maximum VREF pin leakage current from 4 µA to 8 µA.
  • Added information about GPIO Intel FPGA IP version 19.3.0.
  • Added information about OCT Intel FPGA IP version 19.3.0.
2019.04.02 19.1 Initial release.
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