Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Datasheet
Intel® Arria® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Arria® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications HPS Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Specifications x
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance HPS PLL Output Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Arria® 10 Device Datasheet

Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices

Table 30.  Reference Clock Specifications
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O Standards Dedicated reference clock pin CML, Differential LVPECL, LVDS, and HCSL
RX reference clock pin CML, Differential LVPECL, and LVDS

Input Reference Clock Frequency

(CMU PLL)

   61 — 800 MHz

Input Reference Clock Frequency

(ATX PLL)

   100 — 800 MHz

Input Reference Clock Frequency

(fPLL PLL)

  

25 44 /

50 45

— 800 MHz
Rise time 20% to 80% — — 400 ps
Fall time 80% to 20% — — 400 ps
Duty cycle — 45 — 55 %
Spread-spectrum modulating clock frequency PCIe 30 — 33 kHz
Spread-spectrum downspread PCIe — 0 to –0.5 — %
On-chip termination resistors — — 100 — Ω
Absolute VMAX Dedicated reference clock pin — — 1.6 V
RX reference clock pin — — 1.2 V
Absolute VMIN — –0.4 — — V
Peak-to-peak differential input voltage — 200 — 1600 mV
VICM (AC coupled) VCCR_GXB = 0.95 V — 0.95 — V
VCCR_GXB = 1.03 V — 1.03 — V
VCCR_GXB = 1.12 V — 1.12 — V
VICM (DC coupled) HCSL I/O standard for PCIe reference clock 250 — 550 mV
Transmitter REFCLK Phase Noise (622 MHz) 46 100 Hz — — –70 dBc/Hz
1 kHz — — –90 dBc/Hz
10 kHz — — –100 dBc/Hz
100 kHz — — –110 dBc/Hz
≥ 1 MHz — — –120 dBc/Hz
Transmitter REFCLK Phase Jitter (100 MHz) 1.5 MHz to 100 MHz (PCIe) — — 4.2 ps (rms)
RREF — — 2.0 k ±1% — Ω
TSSC-MAX-PERIOD-SLEW Max SSC df/dt     0.75  
Table 31.  Transceiver Clocks Specifications
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
CLKUSR pin for transceiver calibration Transceiver Calibration 100 — 125 MHz
reconfig_clk Reconfiguration interface 100 — 125 MHz
Table 32.  Transceiver Clock Network Maximum Data Rate Specifications
Clock Network Maximum Performance 47 Channel Span Unit
ATX fPLL CMU
x1 17.4 12.5 10.3125 6 channels in a single bank Gbps
x6 17.4 12.5 N/A 6 channels in a single bank Gbps
PLL feedback compensation mode 17.4 12.5 N/A Side-wide Gbps
xN at 0.95 V VCCR_GXB/VCCT_GXB 10.5 10.5 N/A Up two banks and down two banks 47 48 Gbps
xN at 1.03 V VCCR_GXB/VCCT_GXB 15.0 12.5 N/A Up two banks and down two banks47 48 Gbps
xN at 1.12 V VCCR_GXB/VCCT_GXB 16.0 12.5 N/A Up two banks and down two banks47 48 Gbps
Table 33.  Receiver Specifications
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O Standards — High Speed Differential I/O, CML , Differential LVPECL , and LVDS 49
Absolute VMAX for a receiver pin 50 — — — 1.2 V
Absolute VMIN for a receiver pin 50 — -0.4 — — V
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration — — — 1.6 V
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration VCCR_GXB = 1.12 V — — 2.0 V
VCCR_GXB = 1.03 V — — 2.0 V
VCCR_GXB = 0.95 V — — 2.4 V
Minimum differential eye opening at receiver serial input pins 51 — 50 — — mV
Differential on-chip termination resistors 85-Ω setting — 85 ± 30% — Ω
100-Ω setting — 100 ± 30% — Ω
VICM (AC and DC coupled) 52 VCCR_GXB = 0.95 V — 600 — mV
VCCR_GXB = 1.03 V — 700 — mV
VCCR_GXB = 1.12 V — 700 — mV
tLTR 53 — — — 10 µs
tLTD 54 — 4 — — µs
tLTD_manual 55 — 4 — — µs
tLTR_LTD_manual 56 — 15 — — µs
Run Length — — — 200 UI
CDR PPM tolerance PCIe-only -300 — 300 PPM
All other protocols -1000 — 1000 PPM
Programmable DC Gain Setting = 0-4 0 — 10 dB
Programmable AC Gain at High Gain mode and Data Rate ≤ 6 Gbps with 0.95 V VCCR Setting = 0-28 0 — 19 dB
Programmable AC Gain at High Gain mode and Data Rate ≤ 6 Gpbs with 1.03 V VCCR Setting = 0-28 0 — 21 dB
Programmable AC Gain at High Gain mode and Data Rate ≤ 17.4 Gpbs with 1.03 V VCCR Setting = 0-28 0 — 17 dB
Programmable AC Gain at High Data Rate mode Setting = 0-15 0 — 8 dB
Table 34.  Transmitter Specifications
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O Standards — High Speed Differential I/O 57 —
Differential on-chip termination resistors 85-Ω setting — 85 ± 20% — Ω
100-Ω setting — 100 ± 20% — Ω
VOCM (AC coupled) VCCT = 0.95 V — 450 — mV
VCCT = 1.03 V — 500 — mV
VCCT = 1.12 V — 550 — mV
VOCM (DC coupled) VCCT = 0.95 V — 450 — mV
VCCT = 1.03 V — 500 — mV
VCCT = 1.12 V — 550 — mV
Rise time 58 20% to 80% 20 — 130 ps
Fall time 58 80% to 20% 20 — 130 ps
Intra-differential pair skew 59 TX VCM = 0.5 V and slew rate setting of SLEW_R5 60 — — 15 ps
Table 35.  Typical Transmitter VOD Settings
Symbol VOD Setting VOD-to-VCCT Ratio
VOD differential value = VOD-to-VCCT ratio x VCCT 31 1.00
30 0.97
29 0.93
28 0.90
27 0.87
26 0.83
25 0.80
24 0.77
23 0.73
22 0.70
21 0.67
20 0.63
19 0.60
18 0.57
17 0.53
16 0.50
15 0.47
14 0.43
13 0.40
12 0.37
Table 36.  Transmitter Channel-to-channel Skew Specifications
Mode Channel Span Maximum Skew Unit
x6 Clock Up to 6 channels in one bank 61 ps
xN Clock Within 2 banks 230 ps
Up 2 banks and down 2 banks 500
PLL Feedback Compensation 61, 62, 63 Side-wide 1600 ps
Related Information
44 This specification is for HDMI mode only.
45 This specification is for other non-HDMI modes.
46 To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622).
47 The maximum data rate depends on speed grade.
48 For more information, refer to the PLLs and Clock Networks chapter of the Intel® Arria® 10 Transceiver PHY User Guide.
49 CML, Differential LVPECL, and LVDS are only used on AC coupled links.
50 The device cannot tolerate prolonged operation at this absolute maximum.
51 The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
52 Intel® Arria® 10 devices only support DC coupling when using the Hybrid Memory Cube (HMC) or the Intel QuickPath Interconnect (QPI) specifications.
53 tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
54 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
55 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.
56 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.
57 High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel® Arria® 10 transceivers.
58 The Intel® Quartus® Prime software automatically selects the appropriate slew rate depending on the design configurations.
59 In QPI mode, if VCM < 0.17 V, the input Vid must be greater than 100 mV. If VCM > 0.17 V, the input Vid must be greater than 70 mV.
60 SLEW_R1 is the slowest and SLEW_R5 is the fastest. SLEW_R6 and SLEW_R7 are not used.
61 refclk is set to 125 MHz during the test.
62 You can reduce the lane-to-lane skew by increasing the reference clock frequency.
63 The middle refclk location provides the lowest lane-to-lane skew.
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