Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Datasheet
Intel® Arria® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Arria® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications HPS Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Specifications x
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance HPS PLL Output Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Arria® 10 Device Datasheet

Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 67.  Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) TX_CLK clock period — 8 — ns
Tclk (100Base-T) TX_CLK clock period — 40 — ns
Tclk (10Base-T) TX_CLK clock period — 400 — ns
Tdutycycle TX_CLK duty cycle 45 50 55 %
Td 100 TX_CLK to TXD/TX_CTL output data delay –0.5 — 0.5 ns
Figure 13. RGMII TX Timing Diagram
Table 68.  RGMII RX Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) RX_CLK clock period — 8 — ns
Tclk (100Base-T) RX_CLK clock period — 40 — ns
Tclk (10Base-T) RX_CLK clock period — 400 — ns
Tsu RX_D/RX_CTL setup time 1 — — ns
Th 101 RX_D/RX_CTL hold time 1 — — ns
Figure 14. RGMII RX Timing Diagram
Table 69.  Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Typ Max Unit
Tclk (100Base-T) TX_CLK clock period — 20 — ns
Tclk (10Base-T) TX_CLK clock period — 20 — ns
Tdutycycle Clock duty cycle, internal clock source 35 50 65 %
Tdutycycle Clock duty cycle, external clock source 35 50 65 %
Table 70.  RMII TX Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Typ Max Unit
Td TX_CLK to TXD/TX_CTL output data delay 7 — 10 ns
Table 71.  RMII RX Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Typ Max Unit
Tsu RX_D/RX_CTL setup time 1 — — ns
Th RX_D/RX_CTL hold time 0.4 — — ns
Table 72.  Management Data Input/Output (MDIO) Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Typ Max Unit
Tclk MDC clock period — 400 — ns
Td MDC to MDIO output data delay 10.2 — 20 ns
Tsu Setup time for MDIO data 10 — — ns
Th Hold time for MDIO data 0 — — ns
Figure 15. MDIO Timing Diagram
Related Information
100 Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
101 For more information, refer to the Intel® Arria® 10 SoC Device Design Guidelines.
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