Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Datasheet
Intel® Arria® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Arria® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications HPS Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Specifications x
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance HPS PLL Output Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Arria® 10 Device Datasheet

I/O PLL Specifications

Table 39.  I/O PLL Specifications for Intel® Arria® 10 Devices
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency –1 speed grade 10 — 800 68 MHz
–2 speed grade 10 — 700 68 MHz
–3 speed grade 10 — 650 68 MHz
fINPFD Input clock frequency to the PFD — 10 — 325 MHz
fCASC_INPFD Input clock frequency to the PFD of destination cascade PLL — 10 — 60 MHz
fVCO PLL VCO operating range –1 speed grade 600 — 1600 MHz
–2 speed grade 600 — 1434 MHz
–3 speed grade 600 — 1250 MHz
fCLBW PLL closed-loop bandwidth — 0.1 — 8 MHz
tEINDUTY Input clock or external feedback clock input duty cycle — 40 — 60 %
fOUT Output frequency for internal global or regional clock (C counter) –1, –2, –3 speed grade — — 644 MHz
fOUT_EXT Output frequency for external clock output –1 speed grade — — 800 MHz
–2 speed grade — — 720 MHz
–3 speed grade — — 650 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) Non-SmartVID 45 50 55 %
SmartVID 42 50 58 %
tFCOMP External feedback clock compensation time — — — 10 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk — — — 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms
tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on the areset signal — 10 — — ns
tINCCJ 69 70 Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.15 UI (p-p)
FREF < 100 MHz — — 750 ps (p-p)
tOUTPJ_DC Period jitter for dedicated clock output FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
tOUTCCJ_DC Cycle-to-cycle jitter for dedicated clock output FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
tOUTPJ_IO 71 Period jitter for clock output on the regular I/O FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
tOUTCCJ_IO 71 Cycle-to-cycle jitter for clock output on the regular I/O FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
tCASC_OUTPJ_DC Period jitter for dedicated clock output in cascaded PLLs FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
Related Information
68 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
69 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
70 FREF is fIN/N, specification applies when N = 1.
71 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel® Arria® 10 Devices table.
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