Intel® Arria® 10 Device Datasheet

Download PDF
ID 683771
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Datasheet
Intel® Arria® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Arria® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications HPS Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Specifications x
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance HPS PLL Output Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Arria® 10 Device Datasheet

FPP Configuration Timing when DCLK-to-DATA[] >1

Table 80.  FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel® Arria® 10 DevicesUse these timing parameters when you use the decompression and design security features.
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 1,440 ns
tCF2ST0 nCONFIG low to nSTATUS low — 960 ns
tCFG nCONFIG low pulse width 2 — μs
tSTATUS nSTATUS low pulse width 268 3,000 121 μs
tCF2ST1 nCONFIG high to nSTATUS high — 3,000 121 μs
tCF2CK 122 nCONFIG high to first rising edge on DCLK 3,010 — μs
tST2CK 122 nSTATUS high to first rising edge of DCLK 10 — μs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time after rising edge on DCLK N–1/fDCLK 123 — s
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX DCLK frequency (FPP ×8/×16/×32) — 100 MHz
tCD2UM CONF_DONE high to user mode 124 175 830 μs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU +
(600 × CLKUSR period) — —
Related Information
121 You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
122 If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
123 N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating.
124 The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
Level Two Title