Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Datasheet
Intel® Arria® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Arria® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications HPS Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Specifications x
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance HPS PLL Output Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Arria® 10 Device Datasheet

Transceiver Power Supply Operating Conditions

Table 4.  Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GX/SX Devices
Symbol Description Condition 17 Minimum 18 Typical Maximum 18 Unit
VCCT_GXB [L1,R4] [C, D, E, F, G, H, I, J] 19 Transmitter power supply Chip-to-Chip ≤ 17.4 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.0 1.03 1.06 V
Chip-to-Chip ≤ 11.3 Gbps 0.92 0.95 0.98 V
VCCR_GXB[L1,R4] [C, D, E, F, G, H, I, J] 19 Receiver power supply Chip-to-Chip ≤ 17.4 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.0 1.03 1.06 V
Chip-to-Chip ≤ 11.3 Gbps 0.92 0.95 0.98 V
VCCH_GXB[L,R] Transceiver output buffer power supply — 1.710 1.8 1.890 V
Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-side basis to minimize power consumption. Refer to the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines and the Intel® Quartus® Prime pin report for information about pinning out the package to minimize power consumption for your specific design.
Table 5.  Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GT Devices
Symbol Description Condition 21 Minimum 18 Typical Maximum 18 Unit
VCCT_GXB[L,R] Transmitter power supply Chip-to-Chip ≤ 25.8 Gbps 22

Or

Backplane 20 ≤ 12.5 Gbps

1.10 1.12 1.14 V
Chip-to-Chip ≤ 15 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.0 1.03 1.06 V
Chip-to-Chip ≤ 11.3 Gbps 0.92 0.95 0.98 V
VCCR_GXB[L,R] Receiver power supply Chip-to-Chip ≤ 25.8 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.10 1.12 1.14 V
Chip-to-Chip ≤ 15 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.0 1.03 1.06 V
Chip-to-Chip ≤ 11.3 Gbps 0.92 0.95 0.98 V
VCCH_GXB[L,R] Transceiver output buffer power supply — 1.710 1.8 1.890 V
Related Information
17 These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Intel® Arria® 10 GX/SX Devices for exact data rate ranges.
18 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
19 To support PCIe* Gen3, this pin must be 1.03 V (± 30 mV) or higher.
20 Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
21 These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Intel® Arria® 10 GT Devices table for exact data rate ranges.
22 25.8 Gbps is the maximum data rate for GT channels. 17.4 Gbps is the maximum data rate for GX channels.
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