Intel® Arria® 10 Device Datasheet

Download PDF
ID 683771
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Datasheet
Intel® Arria® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Arria® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications HPS Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Specifications x
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance HPS PLL Output Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Arria® 10 Device Datasheet

Absolute Maximum Ratings

This section defines the maximum operating conditions for Intel® Arria® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

CAUTION:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Table 1.  Absolute Maximum Ratings for Intel® Arria® 10 Devices
Symbol Description Condition Minimum Maximum Unit
VCC Core voltage power supply — –0.50 1.21 V
VCCP Periphery circuitry and transceiver fabric interface power supply — –0.50 1.21 V
VCCERAM Embedded memory power supply — –0.50 1.36 V
VCCPT Power supply for programmable power technology and I/O pre-driver — –0.50 2.46 V
VCCBAT Battery back-up power supply for design security volatile key register — –0.50 2.46 V
VCCPGM Configuration pins power supply 1 –0.50 2.46 V
VCCIO I/O buffers power supply 3 V I/O –0.50 4.10 V
LVDS I/O –0.50 2.46 V
VCCA_PLL Phase-locked loop (PLL) analog power supply — –0.50 2.46 V
VCCT_GXB Transmitter power supply — –0.50 1.34 V
VCCR_GXB Receiver power supply — –0.50 1.34 V
VCCH_GXB Transceiver output buffer power supply — –0.50 2.46 V
VCCL_HPS HPS core voltage and periphery circuitry power supply — –0.50 1.27 V
VCCIO_HPS HPS I/O buffers power supply 3 V I/O –0.50 4.10 V
LVDS I/O –0.50 2.46 V
VCCIOREF_HPS HPS I/O pre-driver power supply — –0.50 2.46 V
VCCPLL_HPS HPS PLL power supply — –0.50 2.46 V
IOUT DC output current per pin — –25 2 3 4 5 6 25 mA
TJ Operating junction temperature — –55 125 °C
TSTG Storage temperature (no bias) — –65 150 °C
Related Information
1 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
2 The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA.
3 Total current per LVDS I/O bank must not exceed 100 mA.
4 Voltage level must not exceed 1.89 V.
5 Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os.
6 Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power sequencing requirement. For more details, refer to AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 Devices and Power Management in Intel® Arria® 10 Devices chapter.
Level Two Title