Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Datasheet
Intel® Arria® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Arria® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications HPS Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Specifications x
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance HPS PLL Output Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Arria® 10 Device Datasheet

SPI Timing Characteristics

Table 63.  SPI Master Timing Requirements for Intel® Arria® 10 DevicesYou can adjust the input delay timing by programming the rx_sample_dly register.
Symbol Description Min Typ Max Unit
Tclk SPI_CLK clock period 16.67 — — ns
Tdutycycle SPI_CLK duty cycle 45 50 55 %
Tdssfrst 91 SPI_SS asserted to first SPI_CLK edge 1.5 × TSPI_CLK – 2 — — ns
Tdsslst 91 Last SPI_CLK edge to SPI_SS deasserted TSPI_CLK – 2 — — ns
Tdio Master-out slave-in (MOSI) output delay –1 — 1 ns
Tsu 92 Input setup in respect to SPI_CLK capture edge 16 – (rx_sample_dly × Tspi_ref_clk) 93 94 — — ns
Th 92 Input hold in respect to SPI_CLK capture edge 0 — — ns
Tdssb2b Minimum delay of slave select deassertion between two back-to-back transfers (frames) 1 — — SPI_CLK
Figure 7. SPI Master Output Timing Diagram
Figure 8. SPI Master Input Timing Diagram
Table 64.  SPI Slave Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Typ Max Unit
Tclk SPI_CLK clock period 20 — — ns
Tdutycycle SPI_CLK duty cycle 45 50 55 %
Ts SPI slave input setup time 5 — — ns
Th SPI slave input hold time 8 — — ns
Tsuss SPI_SS asserted to first SCLK_IN edge 5 — — ns
Thss Last SCLK_IN edge to SPI_SS deasserted 5 — — ns
Td Master-in slave-out (MISO) output delay 2 × Tspi_ref_clk + 5.3 95 — 3 × Tspi_ref_clk + 11.8 95 ns
Figure 9. SPI Slave Output Timing Diagram
Figure 10. SPI Slave Input Timing Diagram
91 SPI_SS behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
92 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.
93 A rx_sample_dly value of 0 is an invalid setting.
94 SPI_REF_CLK is the internal reference clock of the SPI Slave, which is l4_main_clk.
95 SPI_REF_CLK is the internal reference clock of the SPI Slave, which is l4_main_clk.
Level Two Title