E-Tile Transceiver PHY User Guide

ID 683723
Date 7/08/2024
Public
Document Table of Contents

9.5.33. rsfec_corr_1s_cnt (High)

Register Name Description Address Addressing Mode
rsfec_corr_1s_cnt_0_hi RS-FEC number of bits corrected 1->0 for the lane (high word: bits 63 to 32) 0x284 32-bits
rsfec_corr_1s_cnt_1_hi 0x28C
rsfec_corr_1s_cnt_2_hi 0x294
rsfec_corr_1s_cnt_3_hi 0x29C
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
31:0 stat Statistics value.

RO

WO

-

0x0000 0000