CPRI Intel® FPGA IP User Guide

Download PDF
ID 683595
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP 2. Getting Started with the CPRI Intel® FPGA IP 3. CPRI IP Functional Description 4. CPRI Intel® FPGA IP Signals 5. CPRI Intel® FPGA IP Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support 1.3. Intel® FPGA IP Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP 1.5. CPRI IP Release Information
1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI Intel® FPGA IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP x
2.1. Installation and Licensing 2.2. Generating aCPRI Intel® FPGA IP 2.3. CPRI Intel® FPGA IP Generated Files 2.4. CPRI Intel® FPGA IP Parameters 2.5. Integrating the CPRI IP into your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Running the CPRI IP Design Example 2.8. CPRI Design Example Clocks 2.9. About the Testbench 2.10. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating the CPRI IP into your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. CPRI IP Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
2.5.7. Reference and System PLL Clock for your IP Design x
2.5.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.5.7.2. System PLL Connections for the Agilex 5 Variations 2.5.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP
2. Getting Started with the CPRI Intel® FPGA IP
3. CPRI IP Functional Description
4. CPRI Intel® FPGA IP Signals
5. CPRI Intel® FPGA IP Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

3.4. Start-Up Sequence Following Reset

After reset, if you turned on Enable start-up sequence state machine in the CPRI IP core, the internal state machine performs link synchronization and other initialization tasks. If you did not turn on Enable start-up sequence state machine, user logic should perform these functions.

Figure 26. Start-up states and transitions Figure From CPRI v7.0 Specification With Intel® FPGA IP Core AdditionsStates and transitions marked in black are from the CPRI v7.0 specification Figure 30: Start-up states and transitions. Additional transitions from State G that the Intel® FPGA IP core implements are marked in blue.

The internal state machine implements the start-up state machine transitions shown in section 4.5.2, Figure 30: Start-up states and transitions, and described in section 4.5.3, in the CPRI specification. In addition, the internal state machine implements the following transitions from State G: Passive Link.

  • If you assert reconfig_reset, the start-up state machine transitions to State A.
  • If the IP core detects any of the following situations, the start-up state machine transitions to State B:
    • Deassertion of reconfig_reset.
    • Loss of signal (LOS). Refer to Direct L1 Control and Status Interface and FLSAR Register.
    • Loss of frame (LOF). Refer to Direct L1 Control and Status Interface and FLSAR Register.
    • Remote alarm indication (RAI). Refer to Direct L1 Control and Status Interface and FLSAR Register.
    • L1 start-up timer expiration. If you turn on Enable start-up sequence state machine option, the IP core responds to both the nego_l1_timer_expired port and startup_timer_expired field of the START_UP_SEQ register at offset 0x24.
  • When HFNSYNC = 1, either read from the L1_STATUS_REGISTER offset 0x04 or from state_l1_sync[2:0], set nego_bitrate_complete_1. Then, the start-up state machine transitions from B to C.
  • If the IP core detects that protocol negotiation is complete, the start-up state machine transitions to State C. The IP core detects that protocol negotiation is not complete if the following conditions hold:
    • You set nego_protocol_complete signal to 0 when you turn off Enable protocol version and C&M channel setting auto-negotiation option, or
    • nego_protocol_complete field of the START_UP_SEQ register at offset 0x24 has the value of 0, or
    • Slave protocol version does not match the protocol version of the CPRI master. Specifically, the rx_prot_ver and tx_prot_ver fields of the PROT_VER register at offset 0x10 have different values. When you turn on Enable protocol version and C&M channel setting auto-negotiation option, the IP core allows deframer to detect the incoming protocol version to the rx_prot_ver, and compare it to the proposed tx_prot_ver. If they are different, IP core detects that protocol negotiation is not complete. With this option ON, you can tie nego_protocol_complete input port to 0. Internally, it is set to 1 once the protocol negotiation is completed.
  • When in State C, either of the following condition moves to State D:
    • When you turn on Enable protocol version and C&M channel setting auto-negotiation (prot_ver_auto sets to 1), the IP core allows deframer to detect the incoming protocol version to the rx_prot_ver, and compare it to the proposed tx_prot_ver. If the value matches, it will set nego_protocol_complete to 1 internally, the nego_protocol_complete can be tie off to 0 externally.
    • If Enable protocol version and C&M channel setting auto-negotiation is disabled. You must manually change the PROT_VER[7:0] register offset 0x10 tx_prot_ver each iteration (you can wait for few milisecond before changing to new value of 2 or 1) until read back for rx_prot_ver_valid is 1, then drive the nego_protocol_complete to 1.
  • If the IP core detects that control and management negotiation is complete, the start-up state machine transitions to State D. The IP core detects that control and management negotiation is not complete if the following conditions hold:
    • You set nego_protocol_complete signal to 0 when you turn off Enable protocol version and C&M channel setting auto-negotiation option, or
    • nego_cm_complete field of the START_UP_SEQ register at offset 0x24 has the value of 0, or
    • rx_slow_cm_rate_valid field of the CM_STATUS register has the value of 0, and
    • rx_fast_cm_ptr_valid field of the CM_STATUS register has the value of 0.
  • When in State D, the following condition moves to State E:
    • When you turn on Enable protocol version and C&M channel setting auto-negotiation (prot_ver_auto sets to 1), the IP core allows deframer to detect the incoming C&M rate rx_slow_cm_rate and rx_fast_cm_ptr, and compare it to the proposed tx_slow_cm_rate and tx_fast_cm_ptr. If the value matches, it will set nego_protocol_complete to 1 internally, the nego_protocol_complete can be tie off to 0 externally.
    • If Enable protocol version and C&M channel setting auto-negotiation is disabled. You must manually change the CM_CONFIG[5:0] (offset x1C) tx_fast_cm_ptr and/or CM_CONFIG[10:8] (offset x1C) tx_slow_cm_rate, and then poll CM_STATUS (offset 20h) rx_slow_cm_rate_valid or rx_fast_cn_ptr_valid (may be for few hyperframe).
      • If valid is not asserted, change to new value.
      • If valid is asserted, drive nego_cm_complete to 1 (you can wait for few milisecond before changing to new value) until read back for rx_prot_ver_valid is 1, then drive nego_protocol_complete to 1.

        Always start from higher value base on the CPRI Spec 4.2.7.6. L1 Inband Protocol, Z.66.0 for slow C&M, Z.194.0 for Fast C&M.

  • When in State E, the following condition moves to State F:
    • During this state, the negotiation are vendor specific and the CPRI MAC IP core do not support any auto-negotiation. Drive the nego_vss_complete to 1 when the negotiation is completed.

Section Content
Start-Up Sequence Interface Signals

Level Two Title