CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/17/2024
Public
Document Table of Contents

3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes

Figure 14. CPRI Slave IP Core in Hybrid Clocking ModeThe hybrid clocking mode option is not available in IP core variations that target an Intel Stratix 10 E-tile or Agilex® 7 E- tile device.


Note: You must calibrate the transceiver TX PLL used with the CPRI IP connections for optimal performance. If the TX PLL input reference clock is not present, stable, and the correct frequency when the FPGA is configured, it may not be correctly calibrated, In this case you must recalibrate it when the reference clock is correct. Refer to the CPRI IP Transceiver PLL Calibration for more information about the TX PLL calibration.
Figure 15. CPRI Master IP Core in Hybrid Clocking Mode
Figure 16.  CPRI Master IP Core in Internal Clocking Mode for Stratix® 10 L- tile, H-tile, Arria® 10, and V-series Device Variations
Figure 17.  CPRI Master IP Core in Internal Clocking Mode for Stratix® 10 E- tile and Agilex® 7 E- tile Device Variations
Figure 18.  CPRI Slave IP Core in Internal Clocking Mode for Stratix® 10 L- tile, H-tile, Arria® 10, and V-series Device Variations
Figure 19.  CPRI Slave IP Core in Internal Clocking Mode for Stratix® 10 E- tile and Agilex® 7 E- tile Device Variations
Figure 20.  CPRI Slave IP Core in External Clocking Mode for Stratix® 10 L- tile, H-tile, Arria® 10, and V-series Device Variations
Note: For some data rate, you can not connect tx_clkout to cpri_coreclk directly. Example: for 10.1376G data rate, the tx_clkout is 253.46MHz, while the cpri_coreclk requires 307.2MHz.
Figure 21.  CPRI Slave IP Core in External Clocking Mode for Stratix® 10 E-tile and Agilex® 7 E- tile Device Variations
Figure 22.  CPRI Master IP Core in External Clocking Mode for Stratix® 10 L- tile, H-tile, Arria® 10, and V-series Device Variations
Note: For some data rate, you can not connect tx_clkout to cpri_coreclk directly. Example: for 10.1376G data rate, the tx_clkout is 253.46MHz, while the cpri_coreclk requires 307.2MHz.
Figure 23.  CPRI Master IP Core in External Clocking Mode for Stratix® 10 E- tile and Agilex® 7 E- tile Device Variations
Figure 24.  CPRI Slave IP Core in External Clocking Mode with Single-Trip Delay Calibration Feature for Arria® 10 Device Variations Intel® provides the IOPLL and DPCU blocks with the CPRI IP. For correct single-trip delay calibration functionality, you must connect these blocks as shown.