CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/17/2024
Public
Document Table of Contents

3.19.8. Transceiver Debug Interface

Table 50.  Transceiver Debug Interface SignalsThe CPRI Intel® FPGA IP provides a xcvr_rx_is_lockedtodata status signal. If you turn on Enable L1 debug interfaces in the CPRI parameter editor, the IP core provides some additional status signals from the transceiver.

All of the transceiver debug signals are asynchronous.

Signal Name

Direction

Description

xcvr_rx_is_lockedtodata Output Indicates that the receiver CDR is locked to the incoming serial data. This signal is available whether or not you turn on Enable L1 debug interfaces in the parameter editor.
xcvr_rx_is_lockedtoref Output Indicates that the receiver CDR is locked to the xcvr_cdr_refclk reference clock.
xcvr_rx_errdetect[3:0] Output Each bit [n] indicates the receiver has detected an 8B/10B code group violation in byte [n] of the 32-bit data word.
xcvr_rx_disperr[3:0] Output Each bit [n] indicates that the receiver has detected an 8B/10B parity error in byte [n] of the 32-bit data word.
xcvr_rx_blk_sh_err Output Indicates that the receiver has detected a 64B/66B SYNC_HEADER violation.