CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/17/2024
Public
Document Table of Contents

2.9. About the Testbench

Intel® provides a demonstration testbench with the CPRI Intel® FPGA IP.

If you click Generate Example Design in the CPRI parameter editor, the Quartus® Prime software generates the demonstration testbench. The parameter editor prompts you for the desired location of the testbench.

The testbench performs the following sequence of actions with the static DUT. The listed registers offset L1_CONFIG and CM_CONFIG are in word addressing mode.

  1. Starts up CPRI rate.
  2. Enables transmission on the CPRI link by setting the tx_enable bit (bit [0]) of the CPRI IP core L1_CONFIG register at offset 0x8 (and resetting all other fields of the register).
  3. Configures the DUT at the highest possible HDLC bit rate for the CPRI line bit rate, by setting the tx_slow_cm_rate field of the CPRI CM_CONFIG register at offset 0x1C to the appropriate value.
  4. Reads the CM_CONFIG register to confirm settings.
  5. Resynchronizes BFN number if the resynchronization of CPRI radio frame number to a desired value is enabled.
  6. After the DUT and the testbench achieve frame synchronization, executes the following transactions (Only when you turn on corresponding interface in IP parameter editor):
    1. Startup Sequence Finite-State Machine (FSM) with Protocol Version and C&M Auto-Negotiation.
    2. Performs several write transactions to the IQ interface and confirms the testbench receives them on the CPRI link.
    3. Performs several write transactions to the AUX interface and confirms the testbench receives them on the CPRI link.
    4. Performs several write transactions to the Ctrl_AxC interface and confirms the testbench receives them from the DUT on the CPRI link.
    5. Performs several write transactions to the VS interface and confirms the testbench receives them from the DUT on the CPRI link.
    6. Performs several write transactions to the RTVS interface for the 10G variant, and confirms the testbench receives them form the DUT on the CPRI link.
    7. Performs several HDLC transactions and confirms the testbench receives them from the DUT on the CPRI link.
    8. Performs several write transactions to the MI or GMI interface and confirms the testbench receives them from the DUT on the CPRI link.
    9. Performs rate negotiation to new CPRI rate (switches to the next lower bit rate if available, otherwise test ends at the lowest bit rate).
    10. Repeat steps b to i.
Table 19.  Interface Signals
Signal Name Direction Type Description
clk_100 Input 1-Bit Logic 100MHz used for clocking test components, CSR and reset controls.
sampling_refclk Input 1-Bit Logic Reference clock for Agilex® 7 F-Tile IOPLL (Only for Agilex® 7 F-Tile devices).
cdr_refclk Input 1-Bit Logic Reference clock for Core IOPLL, Extended Delay Measurement PLL, and Transceiver.
cdr_refclk1 Input 1-Bit Logic Secondary reference clock for Core IOPLL, Extended Delay Measurement PLL, and Transceiver when rate negotiation is enabled (Only for Stratix® 10 H-Tile or Arria® 10 Devices).
ehip_ref_clk Input 1-Bit Logic Reference clock used to generate high speed serial clocks and data path parallel clocks in CPRI IP (Only for F-Tile and E-Tile devices).
ehip_ref_clk1 Input 1-Bit Logic Secondary reference clock used to generate high speed serial clocks and data path parallel clocks in CPRI IP when rate negotiation is enabled (Only for F-Tileand E-Tile devices).
aib_pll_refclk Input 1-Bit Logic Reference clock for Agilex® 7 F-tile and E-Tile or Stratix® 10 E-Tile AIB PLL (Only for F-Tile and E-Tile devices).
i_refclk_syspll Input 1-Bit Logic Reference clock for Agilex™ 5 system PLL.
i_refclk_xcvr Input 1-Bit Logic Transceiver reference clock for CPRI IP (Only for Agilex™ 5 devices).
reset_n Input 1-Bit Logic Global active-low reset. Not for E-tile, F-tile and Agilex™ 5 devices)
rx_serial Input 1-Bit Logic Receiver serial port.
tx_serial Output 1-Bit Logic Transmitter serial port.