CPRI Intel® FPGA IP User Guide

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ID 683595
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP 2. Getting Started with the CPRI Intel® FPGA IP 3. CPRI IP Functional Description 4. CPRI Intel® FPGA IP Signals 5. CPRI Intel® FPGA IP Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support 1.3. Intel® FPGA IP Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP 1.5. CPRI IP Release Information
1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI Intel® FPGA IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP x
2.1. Installation and Licensing 2.2. Generating aCPRI Intel® FPGA IP 2.3. CPRI Intel® FPGA IP Generated Files 2.4. CPRI Intel® FPGA IP Parameters 2.5. Integrating the CPRI IP into your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Running the CPRI IP Design Example 2.8. CPRI Design Example Clocks 2.9. About the Testbench 2.10. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating the CPRI IP into your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. CPRI IP Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
2.5.7. Reference and System PLL Clock for your IP Design x
2.5.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.5.7.2. System PLL Connections for the Agilex 5 Variations 2.5.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP
2. Getting Started with the CPRI Intel® FPGA IP
3. CPRI IP Functional Description
4. CPRI Intel® FPGA IP Signals
5. CPRI Intel® FPGA IP Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

3.8. Direct Vendor Specific Access Interface

If you turn on Enable direct vendor specific access interface in the CPRI parameter editor, the direct vendor specific access interface is available. This interface allows direct access to the Vendor Specific subchannels in the CPRI hyperframe. The Vendor Specific information is present only in subchannels 16 through (P-1) of the CPRI hyperframe, where P is the Fast C&M pointer value. Check the vs_rx_valid and vs_tx_ready signals to ensure you read and write this interface at the time that corresponds to the correct position in the CPRI frame. If you implement the AUX interface, you can read the value on the aux_rx_x or aux_tx_x output signal to identify the current position in the frame.

This interface is Avalon-ST compliant with a ready latency value of 1.

You can alter the transmit latency with the Auxiliary and direct interfaces write latency cycle(s) parameter.

Table 27.  Direct Vendor Specific Access Interface Signals

All interface signals are clocked by the cpri_clkout clock. The Data path width parameter determines the interface type and width, where N= 32 or 64, C= 3 or 7, and D= 31 or 63.

Direct Vendor Specific RX Interface

Signal Name

Direction

Description

vsN_rx_valid[C:0] Output Each asserted bit indicates the corresponding byte on the current vs_rx_data bus is a valid vendor-specific byte.
vsN_rx_data[D:0] Output Vendor-specific word received from the CPRI frame. The vs_rx_valid signal indicates which bytes are valid vendor-specific bytes.
Direct Vendor Specific TX Interface

Signal Name

Direction

Description

vsN_tx_ready[C:0] Output Each asserted bit indicates the IP core is ready to receive a vendor-specific byte from the corresponding byte of vs_tx_data on the next clock cycle.
vsN_tx_valid[C:0] Input Write valid for vs_tx_data. Assert bit [n] of vs_tx_valid to indicate that byte [n] on the vs_tx_data bus holds a valid value in the current clock cycle.
vsN_tx_data[D:0] Input Vendor-specific word to be written to the CPRI frame. The IP core writes the individual bytes of the current value on the vs_tx_data bus to the CPRI frame based on the vs_tx_ready signal from the previous cycle, and the vs_tx_valid signal in the current cycle.
Figure 42. Direct VS RX Timing DiagramDirect VS RX interface behavior in a CPRI IP core running at 0.6144 Gbps.

The aux_rx_x signal is not part of this interface and is available only if you turn on the AUX interface in your CPRI IP variation. However, its presence in the timing diagram explains the timing of the vs_rx_valid output signal that you use to identify the clock cycles with valid VS data.

The aux_rx_x[7:0] signal (labeled simply aux_rx_x) holds the eight-bit index of the basic frame in the hyperframe, from the perspective of the AUX interface. The subchannel index is the control word index modulo 64, available in aux_rx_x[5:0] if you turn on the AUX interface in your CPRI IP core.



Figure 43. Direct VS TX Timing DiagramExpected behavior on the direct VS TX interface of a CPRI IP core running at 0.6144 Gbps.

The aux_tx_x signal is not part of this interface and is available only if you turn on the AUX interface in your CPRI IP variation. However, its presence in the timing diagram explains the timing of the vs_tx_ready output signal that you use to identify the clock cycles when you can write VS data to the CPRI frame.

The aux_tx_x[7:0] signal (labeled simply aux_tx_x) holds the eight-bit index of the basic frame in the hyperframe, from the perspective of the AUX interface. The subchannel index is the control word index modulo 64, available in aux_tx_x[5:0] if you turn on the AUX interface in your CPRI IP core.

Note that the write latency is one cpri_clkout clock cycle in this example.



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