CPRI Intel® FPGA IP User Guide

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ID 683595
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP 2. Getting Started with the CPRI Intel® FPGA IP 3. CPRI IP Functional Description 4. CPRI Intel® FPGA IP Signals 5. CPRI Intel® FPGA IP Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support 1.3. Intel® FPGA IP Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP 1.5. CPRI IP Release Information
1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI Intel® FPGA IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP x
2.1. Installation and Licensing 2.2. Generating aCPRI Intel® FPGA IP 2.3. CPRI Intel® FPGA IP Generated Files 2.4. CPRI Intel® FPGA IP Parameters 2.5. Integrating the CPRI IP into your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Running the CPRI IP Design Example 2.8. CPRI Design Example Clocks 2.9. About the Testbench 2.10. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating the CPRI IP into your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. CPRI IP Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
2.5.7. Reference and System PLL Clock for your IP Design x
2.5.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.5.7.2. System PLL Connections for the Agilex 5 Variations 2.5.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP
2. Getting Started with the CPRI Intel® FPGA IP
3. CPRI IP Functional Description
4. CPRI Intel® FPGA IP Signals
5. CPRI Intel® FPGA IP Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

2.8. CPRI Design Example Clocks

To run the testbench or synthesizable hardware design example on the supported devices, you must supply the appropriate clock top level (tb_top) input ports with fixed frequencies:

  • clk_100: 100MHz
  • sampling_refclk: 100MHz (Only for the Agilex® 7 F-Tile devices)
  • cdr_refclk:
    • Supply clock with frequency for initial bit rate chosen according to the folllowing table, except for E-Tile, F-tile, and Agilex™ 5 devices.
    • Supply 153.60MHz clock for E-Tile, F-tile and Agilex™ 5 devices. when the IP's Core clock source input is External when generating the example design..
  • cdr_refclk1: Supply secondary clock with frequency for target bit rate according to the folllowing table (Only for the Stratix® 10 H-Tile or Arria® 10 devices when the Rate Negotiation feature is enabled).
    • If selected target bit rate for rate negotiation uses the same reference clock frequency as initial bit rate, supply cdr_refclk and cdr_refclk1 with the same clock frequency.
    • If one or more selected target bit rate for rate negotiation uses different reference clock frequency as initial bit rate, supply cdr_refclk with the frequency required for initial bit rate and supply cdr_refclk1 with the different secondary frequency.
  • ehip_ref_clk: Supply clock with frequency for initial bit rate chosen according to the folllowing table (Only for F-Tile and E-Tile devices).
  • ehip_ref_clk1: Supply secondary clock with frequency for target bit rate according to the folllowing table (Only for F-Tile and E-Tile devices when Rate Negotiation feature is enabled).
    • If selected target bit rate for rate negotiation uses the same reference clock frequency as initial bit rate, supply ehip_ref_clk and ehip_ref_clk1 with the same clock frequency.
    • If one or more selected target bit rate for rate negotiation uses different reference clock frequency as initial bit rate, supply ehip_ref_clk with the frequency required for initial bit rate and supply ehip_ref_clk1 with the different secondary frequency.
  • aib_pll_refclk: 156.25MHz (Only for F-Tile and E-Tile devices).
  • dr_clk_100G_hz: In the Agilex® 7 F-tile devices, this clock is dedicated only for simulation to speed up the NIOS in the dynamic reconfiguration controller. The clock is connected to i_cpu_clk port of the dynamic reconfiguration controller. The two clocks in the dynamic reconfiguration controller are driven as:
    • In design example simulation, i_cpu_clk = 100GHz and i_csr_clk = 100MHz
    • In hardware design example, i_cpu_clk = 100MHz and i_csr_clk = 100MHz
  • i_refclk_syspll: 153.6 MHz. Only for Agilex™ 5 devices.

    i_refclk_xcvr: supply clock with frequency for initial bit rate chosen according to the table. Only for Agilex™ 5 devices).

Table 18.  Reference Clock Frequency Requirement
Initial or Target Bit rate (Mbits/s) i_refclk_xcvr for Agilex™ 5 Devices (MHz) ehip_ref_clk and ehip_ref_clk1 for F-Tile and E-Tile Device (MHz) Other Device (MHz)
24330.24 Unsupported 184.32 253.44
12165.12 184.32 253.44
10137.60 184.32 184.32 253.44
9830.40 Unsupported 153.60 245.76
8110.08 184.32 253.44
6144.00 153.60 245.76
4915.20 153.60 153.60 245.76
3072.00 153.60 245.76
2457.60 153.60 245.76
1228.80 153.60 245.76
614.40 Unsupported 153.60 245.76
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