CPRI Intel® FPGA IP User Guide

Download PDF
ID 683595
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP 2. Getting Started with the CPRI Intel® FPGA IP 3. CPRI IP Functional Description 4. CPRI Intel® FPGA IP Signals 5. CPRI Intel® FPGA IP Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support 1.3. Intel® FPGA IP Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP 1.5. CPRI IP Release Information
1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI Intel® FPGA IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP x
2.1. Installation and Licensing 2.2. Generating aCPRI Intel® FPGA IP 2.3. CPRI Intel® FPGA IP Generated Files 2.4. CPRI Intel® FPGA IP Parameters 2.5. Integrating the CPRI IP into your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Running the CPRI IP Design Example 2.8. CPRI Design Example Clocks 2.9. About the Testbench 2.10. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating the CPRI IP into your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. CPRI IP Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
2.5.7. Reference and System PLL Clock for your IP Design x
2.5.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.5.7.2. System PLL Connections for the Agilex 5 Variations 2.5.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP
2. Getting Started with the CPRI Intel® FPGA IP
3. CPRI IP Functional Description
4. CPRI Intel® FPGA IP Signals
5. CPRI Intel® FPGA IP Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

3.2. CPRI Intel® FPGA IP Clocking Structure

Figure 13.  CPRI Intel® FPGA IP Clocking StructureShows the clocks and clock domains in the CPRI IP. Clock domains are cpri_clkout, clk_ex_delay, cpu_clk, and mii_{rx,tx}clk. The external clean-up PLL is only required in agent clocking mode. The tx_clkout is only available in external clocking mode, and the xcvr_recovered_clk is only available in agent clocking mode.


The main CPRI IP clock is cpri_clkout.

Table 20.   CPRI Intel® FPGA IP Input Clocks
CPRI Input Clock Information
xcvr_ext_pll_clk or xcvr_ext_pll_clk[1:0]

Clocks the transmitter PMA.

You should drive this input clock with the output of the external TX PLL. The frequency of this clock must be one half of the CPRI line bit rate, multiplied by the local clock division factor. You must configure a PLL IP that can drive the required frequency.

xcvr_cdr_refclk or xcvr_cdr_refclk[1:0] Receiver CDR reference clock. You must drive this clock at the frequency you specified for the Receiver CDR reference clock frequency (MHz) parameter in the CPRI parameter editor. This signal must come from a dedicated transceiver reference clock pin.

If you set the Number of receiver CDR reference clock(s) parameter in the CPRI parameter editor to the value of 2, this clock is two bits wide.

For a two-bit xcvr_cdr_refclk port, drive xcvr_cdr_refclk[0] with the reference clock for the initial CPRI line bit rate, because by default, this clock signal drives the CDR.

The IP supports all CDR reference clock frequencies available in the drop-down menu for the Receiver CDR reference clock frequency (MHz) parameter.

Not available for Agilex™ 5 devices.

pll_refclk0 or pll_refclk TX PLL reference clock input. You must connect this port to dedicated transceiver reference clock pin. This input clock is not present in the CPRI IP top-level. However, it is present on a PLL instantiated outside of the CPRI IP. In Stratix® 10 E-tile and Agilex® 7 E- tile devices, this clock is a reference clock for channel PLL.

pll_refclk0 is an input to TX PLL for Arria® 10 and Stratix® 10 devices.

pll_refclk is an input to TX PLL for V-series devices.

reconfig_clk

In Arria V, Arria V GZ, Cyclone V, and Stratix V variations, clock for the CPRI IP transceiver start-up and reconfiguration.

In Arria® 10 and Stratix® 10 variations, clocks the signals on the CPRI transceiver reconfiguration interface. In these variations, this clock is not present if you turn off all of Enable start-up sequence state machine, Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status registers access, and parameters only available in Arria® 10 variations, Enable line bit rate auto-negotiation, Enable single-trip delay calibration.
Note: You cannot calibrate your PHY, if you disable the Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status registers access parameter.

In variations that target any other supported device family, this clock is not present if you turn off both Enable line bit rate auto-negotiation, Enable start-up sequence state machine.

The supported frequency range of this clock is 100–150 MHz.

ex_delay_clk Clock for extended delay measurement.
latency_sclk Clock for delay measurement through the Stratix® 10 hard FIFO buffers in the PCS and the IP. You can (but need not) drive this clock at the same frequency as ex_delay_clk. This clock is present only in IPs that target Stratix® 10 devices.
cpri_coreclk

In hybrid clocking mode, drives the CPRI IP clock cpri_clkout when the IP is running at the CPRI line bit rate of 8.11008, 10.1376, 12.16512 or 24.33024 Gbps and a clock from the transceiver PHY drives the cpri_clkout at all other rates. In external clocking mode, cpri_coreclk drives cpri_clkout at all CPRI line rates. In internal clocking mode, the clock from transceiver PHY drives cpri_clkout.

The frequency at which you must drive cpri_coreclk depends on the CPRI line bit rate:
CPRI Line Bit Rate (Gbps) cpri_coreclk Frequency O(MHz)
0.6144 15.36
1.2288 30.72
2.4576 61.44
3.0720 76.80
4.9152 122.88
6.1440 153.60
8.11008 245.76
9.8304 245.76
10.1376

153.60 (For Stratix® 10 E-tile and Agilex® 7 E- tile device variations)

307.20 (For all other device variations)

12.16512 184.32
24.33024 368.64

You must drive this clock from the same clock source as the xcvr_ext_pll_clk input signal to the IP.

cpu_clk The clock for the signals on the CPRI CPU interface. Supports any frequency that the device fabric supports.
mii_txclk mii_txclk clock for the MII transmitter interface and mii_rxclk clock for the MII receiver interface. You must drive these clocks at the frequency of 25 MHz or 2.5 MHz to achieve the 100 Mbps or 10 Mbps bandwidth required for this interface.

These clocks are present only if you set the value of Ethernet PCS interface to the value of MII in the CPRI parameter editor.

mii_rxclk
gmii_txclk gmii_txclk clocks the GMII transmitter and gmii_rxclk clocks the GMII receiver. You must drive these clocks at the frequency of 125 MHz to achieve the 1000 Mbps bandwidth required for this interface.

These clocks are present only if you set the value of Ethernet PCS interface to the value of GMII in the CPRI parameter editor.

gmii_rxclk
ehip_clk_403 Single lane TX/RX data path clock. This clock drives the internal TX/RX datapath for the CPRI PHY. Embedded multidie interconnect bridge (EMIB) uses this clock. You need to generate the required frequency 402.83203125 MHz for this port externally by using an E-tile Native PHY IP channel PLL. Refer to Figure: Required External Block for the Stratix® 10 E-tile and Agilex® 7 E- tile Device Variations for more information on connecting a PLL to CPRI IP.

This clock is present only in the IPs that target an Stratix® 10 E-tile and Agilex® 7 E- tile device.

ehip_clk_806 The EMIB uses this clock. You need to generate the required frequency of 805.6640625 MHz for this port externally by using an E-tile Native PHY IP channel PLL.

This clock is present only in the IPs that target an Stratix® 10 E-tile and Agilex® 7 E- tile device.

ehip_ref_clk[4:0] Reference clock used to generate high speed serial clocks and data path parallel clocks.

For rates using 8b/10b encoding, supply 153.6 MHz to this port. For rates using 64b/66b encoding supply 184.32 MHz to this port. When you perform rate switching, you can use both bits and select the clock that the reconfiguration interface uses.

This clock is present only in the IPs that target an Stratix® 10 E-tile and Agilex® 7 E- tile device.

ehip_system_pll_clk_link System PLL clock link port.

Only available in the Agilex® 7 F-tile device variant.

ehip_tx_pll_refclk_link TX PLL reference clock link port.

Only available in the Agilex® 7 F-tile device variant.

ehip_tx_pll_refclk_hs_link TX PLL reference clock link port for high speed rates (rates using the 64B/66B encoding).

Only available in the Agilex® 7 F-tile device variant.

ehip_tx_pll_refclk_ls_link TX PLL reference clock link port for low speed rates (rates using the 8B/10B encoding).

Only available in the Agilex® 7 F-tile device variant.

ehip_rx_cdr_refclk_link RX CDR reference clock link port.

Only available in the Agilex® 7 F-tile device variant.

ehip_rx_cdr_refclk_hs_link RX CDR reference clock link port for high speed rates (rates using the 64B/66B encoding).

Only available in the Agilex® 7 F-tile device variant.

ehip_rx_cdr_refclk_ls_link RX CDR reference clock link port for low speed rates (rates using the 8B/10B encoding).

Only available in the Agilex® 7 F-tile device variant.

refclk_tx_clk

TX PLL reference clock. Only available in Agilex™ 5 devices.

refclk_rx_clk

RX CDR reference clock. Only available in Agilex™ 5 devices.

syspll_clk

System PLL clock to be connected to GTS System PLL Clocks Intel FPGA IP. Only available in Agilex™ 5 devices.

pma_cu_clk

Input clock for control unit component of GTS PMA/FEC direct PHY IP. Only available in Agilex™ 5 devices.

Table 21.   CPRI Intel® FPGA IP Core Output Clocks
CPRI Output Clock Information
cpri_clkout

Host clock for the CPRI IP. In hybrid clocking mode, when the IP is running at the CPRI line bit rate of 8.11008, 10.1376, 12.16512 or 24.33024 Gbps, the cpri_coreclk input clock drives cpri_clkout. At all other CPRI line bit rates, the Tx PCS drives cpri_clkout.

In internal clocking mode, the TX PCS drives the cpri_clkout at all CPRI line bit rates.

In external clocking mode, the cpri_coreclk input clock drives cpri_clkout at all CPRI line bit rates.

The frequency of cpri_clkout depends on the CPRI line bit rate:

CPRI Line Bit Rate (Gbps) cpri_clkout Frequency (MHz)
0.6144 15.36
1.2288 30.72
2.4576 61.44
3.0720 76.80
4.9152 122.88
6.1440 153.60
8.11008 245.76
9.8304 245.76
10.1376

153.60 (For Stratix® 10 E-tile, Agilex™ 5, and Agilex® 7 device variations)

307.20 (For all other device variations)

12.16512 184.32
24.33024 368.64
xcvr_recovered_clk Direct recovered clock from the receiver CDR. Use this output clock to drive the external clean-up PLL when your IP core is in slave mode.

The IP drives this clock from the PCS or the PMA block of the transceiver, depending on the value you set for the Recovered clock source parameter in the CPRI parameter editor.

This clock is present only in CPRI IPs in agent clocking mode that support RX traffic. This clock is not present in CPRI IPs with Operation mode set to the value of TX simplex.

The frequency of recovered clock speed (xcvr_recovered_clk) depends on the CPRI line bit rate.

CPRI Line Bit Rate (Gbps) xcvr_recovered_clk Frequency (MHz)
0.6144 15.36
1.2288
  • 30.72
  • 61.44 9
2.4576
  • 61.44
  • 122.88( 9
3.0720
  • 76.80
  • 153.609
4.9152
  • 122.88 (For all other device variations)
  • 245.76 9
6.1440
  • 153.60
  • 307.20 12
8.11008 220.75
9.8304
  • 245.76
  • 491.5212
10.1376
  • 253.44
  • 158.49
12.16512
  • 304.12
  • 184.3212
24.33024
  • 380.16
  • 368.6412
tx_clkout TX PCS clock. In external clocking mode, you can use this clock to drive the cpri_coreclk input clock. If your IP is configured with the single-trip delay calibration feature, you can use this clock to drive the IOPLL block.
ehip_cdr_lock This signal indicates the data locks the recovered clocks. This signal is only present in the Stratix® 10 E-tile and Agilex® 7 E- tile device variations.

Section Content
Example CPRI Intel FPGA IP Core Clock Connections in Different Clocking Modes

Related Information
9 For Stratix® 10 E-tile, Agilex® 7 and Agilex™ 5 device variations
10
11
12 For Stratix® 10 E-tile and Agilex® 7 device variations
Level Two Title