CPRI Intel® FPGA IP User Guide

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ID 683595
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP 2. Getting Started with the CPRI Intel® FPGA IP 3. CPRI IP Functional Description 4. CPRI Intel® FPGA IP Signals 5. CPRI Intel® FPGA IP Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support 1.3. Intel® FPGA IP Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP 1.5. CPRI IP Release Information
1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI Intel® FPGA IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP x
2.1. Installation and Licensing 2.2. Generating aCPRI Intel® FPGA IP 2.3. CPRI Intel® FPGA IP Generated Files 2.4. CPRI Intel® FPGA IP Parameters 2.5. Integrating the CPRI IP into your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Running the CPRI IP Design Example 2.8. CPRI Design Example Clocks 2.9. About the Testbench 2.10. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating the CPRI IP into your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. CPRI IP Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
2.5.7. Reference and System PLL Clock for your IP Design x
2.5.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.5.7.2. System PLL Connections for the Agilex 5 Variations 2.5.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP
2. Getting Started with the CPRI Intel® FPGA IP
3. CPRI IP Functional Description
4. CPRI Intel® FPGA IP Signals
5. CPRI Intel® FPGA IP Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

1.4. Resource Utilization for CPRI Intel® FPGA IP

Resource utilization changes depending on the parameter settings you specify in the CPRI parameter editor. For example, with every additional interface you enable, the IP requires additional resources to implement the module that supports that interface.

The resource utilization numbers are approximate as the Quartus® Prime Fitter assigns resources based on the entirety of your design. The numbers are from a single run on a simple design. Your results may vary.

Table 4.  Minimum and Maximum IP Variations for Resource Utilization Reporting

The IP core FPGA resource utilization table reports resource utilization for a minimum IP core variation and a maximum IP core variation. Parameters not specified remain at their default values, or their values do not affect resource utilization.

Parameter Variation with Minimum Implementation Variation with Maximum Implementation
Line bit rate 2.457 Gbps 3 / 1.2288 Gbps4 / 0.6144 Gbps 5 Maximum bit rate (device family dependent)
Synchronization mode Host Host
Operation mode TX/RX Duplex TX/RX Duplex
Core clock source input Internal Internal
Enable line bit rate auto-negotiation Off On6 / Off5
Receiver soft buffer depth 4 8
Auxiliary and direct interfaces write latency cycle(s) — 9
Enable interface, for all optional direct interfaces in the L1 Features tab Off On
Ethernet PCS interface NONE GMII
L2 Ethernet PCS Tx/Rx FIFO depth — 11
Enable single-trip delay calibration Off Off
Enable round-trip delay calibration Off On 7
Round-trip delay calibration FIFO depth — 47
Table 5.  CPRI IP Core FPGA Resource UtilizationLists the resources and expected performance for minimum and maximum variations of the CPRI IP core in each supported device family.

For Agilex® 7 E-tile, Stratix® 10, and Arria® 10 devices, the results are obtained using the Quartus® Prime Pro Edition software version 22.3.

For Agilex® 7 F-tile devices, the results are obtained using the Quartus® Prime Pro Edition software version 21.2.

For Agilex™ 5 devices, Intel obtains the results using the Quartus® Prime Pro Edition software version 24.1.

For all other target device families, the results are obtained using the Quartus® Prime Standard Edition software version 17.1.

Intel obtains these numbers by turning on the Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status register access parameter. 7

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus® Prime Fitter Report.
Agilex® 7 Device (with F-tile Transceivers) ALMs Logic Registers M20K Blocks
Minimum (2.457 Gbps CPRI line bit rate) 6300 10800 15
Maximum (24.33024 Gbps CPRI line bit rate) 9100 14100 38
Agilex® 7 Device (with E-tile Transceivers) ALMs Logic Registers M20K Blocks
Minimum (2.457 Gbps CPRI line bit rate) 4100 6600 10
Maximum (24.33024 Gbps CPRI line bit rate) 10300 12400 49
Agilex™ 5 Device ALMs Logic Registers M20K Blocks

Minimum (1.2288 Gbps CPRI line bit rate)

2,700 4,600 5
Maximum (10.1376 Gbps CPRI line bit rate) 3,300 5,200 15
Stratix® 10 Device (with E-tile Transceivers) ALMs Logic Registers M20K Blocks
Minimum (2.457 Gbps CPRI line bit rate) 3900 6600 10
Maximum (24.33024 Gbps CPRI line bit rate) 9300 12500 49
Stratix® 10 Device (with H-and L-tile Transceivers) ALMs Logic Registers M20K Blocks
Minimum (1.2288 Gbps CPRI line bit rate) 1400 2400 3
Maximum (24.33024 Gbps CPRI line bit rate) 16800 29600 50
Arria® 10 Device ALMs Logic Registers M20K Blocks
Minimum (1.2288 Gbps CPRI line bit rate) 1000 2100 2
Maximum (12.16 Gbps CPRI line bit rate) 5500 7800 24

Arria V GX or GT Device

ALMs

Logic Registers

M10K Blocks

Minimum (0.6144 Gbps CPRI line bit rate)

900 1600 6

Maximum (6.144 Gbps CPRI line bit rate)

3200 5000 15

Arria V GZ Device

ALMs

Logic Registers

M20K Blocks

Minimum (0.6144 Gbps CPRI line bit rate)

1000 1600 2

Maximum (9.8304 Gbps CPRI line bit rate)

3300 5100 9

Cyclone V GX or GT Device

ALMs

Logic Registers

M10K Blocks

Minimum (0.6144 Gbps CPRI line bit rate)

900 1600 6

Maximum (4.9512 Gbps CPRI line bit rate)

3100 5000 11

Stratix V GX or GT Device

ALMs

Logic Registers

M20K Blocks

Minimum (0.6144 Gbps CPRI line bit rate)

900 1600 2

Maximum (10.1376 Gbps CPRI line bit rate)

3900 6000 18
Related Information
3 For the Agilex® 7, and Stratix® 10 devices with E-tile.
4 For the Arria® 10, and Stratix® 10 devices with H- and L-tile.
5 For all other device families.
6 For the Arria® 10, Stratix® 10, and Agilex® 7 devices with E-tile.
7 Not applicable for Agilex™ 5 devices
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