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2.1. Installation and Licensing
2.2. Generating aCPRI Intel® FPGA IP
2.3. CPRI Intel® FPGA IP Generated Files
2.4. CPRI Intel® FPGA IP Parameters
2.5. Integrating the CPRI IP into your Design: Required External Blocks
2.6. Simulating Intel FPGA IP Cores
2.7. Running the CPRI IP Design Example
2.8. CPRI Design Example Clocks
2.9. About the Testbench
2.10. Compiling the Full Design and Programming the FPGA
2.5.1. Adding the Transceiver TX PLL IP Core
2.5.2. Adding the Reset Controller
2.5.3. Adding the Transceiver Reconfiguration Controller
2.5.4. Adding the Off-Chip Clean-Up PLL
2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks
2.5.6. CPRI IP Transceiver PLL Calibration
2.5.7. Reference and System PLL Clock for your IP Design
3.1. Interfaces Overview
3.2. CPRI Intel® FPGA IP Clocking Structure
3.3. CPRI Intel® FPGA IP Core Reset Requirements
3.4. Start-Up Sequence Following Reset
3.5. AUX Interface
3.6. Direct IQ Interface
3.7. Ctrl_AxC Interface
3.8. Direct Vendor Specific Access Interface
3.9. Real-Time Vendor Specific Interface
3.10. Direct HDLC Serial Interface
3.11. Direct L1 Control and Status Interface
3.12. L1 Debug Interface
3.13. Media Independent Interface (MII) to External Ethernet Block
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block
3.15. CPU Interface to CPRI Intel® FPGA IP Registers
3.16. Auto-Rate Negotiation
3.17. Extended Delay Measurement
3.18. Deterministic Latency and Delay Measurement and Calibration
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces
3.20. Testing Features
3.19.1. CPRI Link
3.19.2. Main Transceiver Clock and Reset Signals
3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface
3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface
3.19.5. RS-FEC Interface
3.19.6. Interface to the External Reset Controller
3.19.7. Interface to the External PLL
3.19.8. Transceiver Debug Interface
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3.18.5. Delay Calibration Features
The CPRI Intel® FPGA IP provides multiple calibration features to support compliance with the CPRI Specification.
- If you turn on Enable single-trip delay calibration in the CPRI parameter editor, supports single-trip delay calibration using the DELAY_CAL_STD_CTRL1, DELAY_CAL_STD_CTRL2, DELAY_CAL_STD_CTRL3, DELAY_CAL_STD_CTRL3, DELAY_CAL_STD_CTRL4, DELAY_CAL_STD_CTRL5, and DELAY_CAL_STD_STATUS registers. You can connect the IOPLL and DPCU blocks that Intel® provides with the CPRI IP core to ensure correct calibration results.
- If you turn on Enable round-trip delay calibration in the CPRI parameter editor, supports round-trip delay calibration using the DELAY_CAL_RTD register.
- In all supported device families, increases the consistency of the round-trip delay using the XCVR_BITSLIP register.