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2.1. Installation and Licensing
2.2. Generating aCPRI Intel® FPGA IP
2.3. CPRI Intel® FPGA IP Generated Files
2.4. CPRI Intel® FPGA IP Parameters
2.5. Integrating the CPRI IP into your Design: Required External Blocks
2.6. Simulating Intel FPGA IP Cores
2.7. Running the CPRI IP Design Example
2.8. CPRI Design Example Clocks
2.9. About the Testbench
2.10. Compiling the Full Design and Programming the FPGA
2.5.1. Adding the Transceiver TX PLL IP Core
2.5.2. Adding the Reset Controller
2.5.3. Adding the Transceiver Reconfiguration Controller
2.5.4. Adding the Off-Chip Clean-Up PLL
2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks
2.5.6. CPRI IP Transceiver PLL Calibration
2.5.7. Reference and System PLL Clock for your IP Design
3.1. Interfaces Overview
3.2. CPRI Intel® FPGA IP Clocking Structure
3.3. CPRI Intel® FPGA IP Core Reset Requirements
3.4. Start-Up Sequence Following Reset
3.5. AUX Interface
3.6. Direct IQ Interface
3.7. Ctrl_AxC Interface
3.8. Direct Vendor Specific Access Interface
3.9. Real-Time Vendor Specific Interface
3.10. Direct HDLC Serial Interface
3.11. Direct L1 Control and Status Interface
3.12. L1 Debug Interface
3.13. Media Independent Interface (MII) to External Ethernet Block
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block
3.15. CPU Interface to CPRI Intel® FPGA IP Registers
3.16. Auto-Rate Negotiation
3.17. Extended Delay Measurement
3.18. Deterministic Latency and Delay Measurement and Calibration
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces
3.20. Testing Features
3.19.1. CPRI Link
3.19.2. Main Transceiver Clock and Reset Signals
3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface
3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface
3.19.5. RS-FEC Interface
3.19.6. Interface to the External Reset Controller
3.19.7. Interface to the External PLL
3.19.8. Transceiver Debug Interface
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3.18.5.1. Single-Trip Delay Calibration
The CPRI Intel® FPGA IP provides an optional mechanism to support calibrating the total delay through a CPRI master and slave on the downlink in a single hop.
If you turn on Enable single-trip delay calibration in the CPRI parameter editor, the CPRI IP and IOPLL and dynamic phase control unit (DPCU) blocks work together to adjust the delay through the RE slave Rx path in response to information about the delay through the REC or RE master Tx path.
Figure 63. Downlink Slave Delay Adjustment for Single-Trip Delay Calibration
The feature introduces the new delay to maintain a single-trip delay measurement as close as possible to the desired single-trip delay you provide to the CPRI IP. The application can also provide Tx path delay information that is appropriate for other use scenarios. For example, you might want to adjust the latency to the synchronization SAP to compensate for the IQ mapper requirements in your system. Refer to the Intel FPGA Wiki CPRI Intel® FPGA IP v6 Latency Formula and Calculation Example.
Figure 64. Single-Trip Delay Does Not Affect Link Delay
The cal_cycle_delay and cal_step_delay fields of the DELAY_CAL_STD_CTRL2 register in the CPRI link slave hold the anticipated delay that you program. The cal_current_delay field of the DELAY_CAL_STD_STATUS register in the CPRI link slave holds the total actual variable delay measurement in the single trip from the synchronization SAP in the CPRI link master to the synchronization SAP in the current CPRI link slave. You can manually specify a consistency check whenever you want, or you can specify that the IP core should run a consistency check once every hyperframe.
If you turn on single-trip delay calibration by setting the cal_en bit in the DELAY_CAL_STD_CTRL1 register, the single-trip calibration feature is active. The user programs the cal_cycle_delay and cal_step_delay fields with the number of whole and fractional cpri_clkout cycles of single-trip variable delay that the system requires. After each consistency check, the CPRI slave IP core adjusts the Rx delay to compensate for mismatches between the programmed, required single-trip delay and the actual single-trip variable delay recorded in the cal_current_delay register field. The delay adjustment mechanism is dynamic phase shifting of the cpri_coreclk.
The slave IP core requires the master IP core measured Tx delay information to calculate the cal_current_delay value. The master IP core sends this information to its downlink slave by one of two possible mechanisms. You program the master IP core DELAY_CAL_STD4 register to specify whether the master sends this information in the incoming hyperframe (and at which location in the hyperframe) or the system writes it in the dedicated slave IP core DELAY_CAL_STD_CTRL5 register. You program the slave IP core DELAY_CAL_STD3 register to specify whether the slave receives this information in the incoming hyperframe (and at which location in the hyperframe) or the system writes it in the dedicated slave DELAY_CAL_STD_CTRL5 register. If both CPRI master and slave are CPRI IP cores, and the register values in the CPRI link master and slave do not match, the single-trip delay calibration does not function correctly. If the CPRI master is not a CPRI IP, the CPRI slave must receive the correct information in the programmed register or hyperframe location.
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