Visible to Intel only — GUID: sam1412833635967
Ixiasoft
Visible to Intel only — GUID: sam1412833635967
Ixiasoft
LVDS SERDES Intel® FPGA IP Transmitter Settings
Parameter | Value | Description |
---|---|---|
TX core registers clock |
|
Selects the clock that clocks the core registers:
This parameter is available only in the TX functional mode. |
Enable tx_coreclock port |
|
Turn on to expose the tx_coreclock port that you can use to drive the core logic feeding the transmitter. The tx_coreclock signal is a feedthrough of the ext_coreclock input. Intel recommends that you use the tx_coreclock output signal if it is requested.
Note: This option is disabled if the Use external PLL option in the PLL Settings tab is turned on. To expose the tx_coreclock when using external PLL, turn off Use external PLL option before turning on the Enable tx_coreclock port. After making changes to Enable tx_coreclock port, you can turn Use external PLL back on.
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Enable tx_outclock port |
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Turn on to expose the tx_outclock port.
Turning on this parameter reduces the maximum number of channels per transmitter interface by one channel. |
Desired tx_outclock phase shift (degrees) | Refer to related information. |
Specifies the phase relationship between the outclock and outgoing serial data in degrees of the LVDS fast clock. |
Actual tx_outclock phase shift (degrees) | Depends on fast_clock and tx_outclock frequencies. Refer to related information. |
Displays the closest achievable tx_outclock phase shift to the desired tx_outclock phase shift. |
Tx_outclock division factor | Depends on the SERDES factor. | Specifies the ratio of the fast clock frequency to the outclock frequency. For example, the maximum number of serial transitions per outclock cycle. |