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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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LVDS Transmitters and Receivers in the Same I/O Bank
If you want to place both LVDS transmitter and receiver interfaces in the same I/O bank, you can use the LVDS SERDES IP core with an external PLL.
- To use an external PLL, in the LVDS SERDES IP parameter editor, turn on the Use external PLL option.
- You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter.
- In each instance, you can use up to the following number of channels:
- 71 transmitters
- 23 DPA or non-DPA receivers
- 12 soft-CDR receivers
- Connect the same PLL to both the transmitter and receiver instances.
Figure 22. LVDS Interface with the IOPLL IP (Non-DPA Mode)This figure shows the connections you need to make between the IOPLL IP and the LVDS SERDES IP in external PLL mode if you are using non-DPA mode.
Figure 23. LVDS Interface with the IOPLL IP (DPA Mode)This figure shows the connections you need to make between the IOPLL IP and the LVDS SERDES IP in external PLL mode if you are using DPA. Invert the locked output port and connect it to the pll_areset port.
Figure 24. LVDS Interface with the IOPLL IP (Soft-CDR Mode)This figure shows the connections you need to make between the IOPLL IP and the LVDS SERDES IP core if you are using soft-CDR mode. Invert the locked output port and connect it to the pll_areset port.