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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
The IP migration flow allows you to migrate the ALTLVDS_TX and ALTLVDS_RX IP cores of Arria® V, Cyclone® V, and Stratix® V devices to the LVDS SERDES IP core of Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
This IP migration flow configures the LVDS SERDES IP core to match the settings of the ALTLVDS_TX and ALTLVDS_RX IP cores, allowing you to regenerate the IP core.
Note: Some IP cores support the IP migration flow in specific modes only. If your IP core is in a mode that is not supported, you may need to run the IP Parameter Editor for the LVDS SERDES IP core and configure the IP core manually.