Visible to Intel only — GUID: sam1412833637387
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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412833637387
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LVDS SERDES IP Core Clock Resource Summary
The Clock Resource Summary tab lists the required frequencies, phase shifts, duty cycles of the required clocks, and instructions for connections. You can refer to this tab for information about configuring and connecting an external PLL to the LVDS SERDES IP core.