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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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LVDS SERDES Intel® FPGA IP General Settings
Parameter | Value | Description |
---|---|---|
Functional mode |
|
Specifies the functional mode of the interface. |
Number of channels |
|
Specifies the number of serial channels in the interface.
For an LVDS RX design, place the refclk pin on the same I/O bank as the receiver. For an LVDS TX design:
|
Data rate | 150.0 to 1600.0 | Specifies the data rate (in Mbps) of a single serial channel. The value is dependent on the Functional mode parameter settings. |
SERDES factor | 3, 4, 5, 6, 7, 8, 9, and 10 | Specifies the serialization rate or deserialization rate for the LVDS interface. |
Use backwards-compatible port names |
|
Turn on to use legacy top-level names that are compatible with the ALTLVDS_TX and ALTLVDS_RX IPs. |