Intel® Quartus® Prime Pro Edition User Guide: Getting Started

Download PDF
ID 683463
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Introduction to Intel® Quartus® Prime Pro Edition 3. Planning FPGA Design for RTL Flow 4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project 5. Working With Intel® FPGA IP Cores 6. Managing Intel® Quartus® Prime Projects A. Next Steps After Getting Started B. Using the Design Space Explorer II C. Document Revision History for Intel® Quartus® Prime Pro Edition User Guide Getting Started D. Intel® Quartus® Prime Pro Edition User Guides
2. Introduction to Intel® Quartus® Prime Pro Edition x
2.1. Before You Begin
2.1. Before You Begin x
2.1.1. Prerequisite Knowledge and Training 2.1.2. Navigate Content Through Tasks 2.1.3. Acronyms
3. Planning FPGA Design for RTL Flow x
3.1. Design Planning 3.2. Selecting the Design Methodology 3.3. Related Trainings
3.1. Design Planning x
3.1.1. Creating a Design Specification and Test Plan 3.1.2. Planning for the Target Device or Board 3.1.3. Planning for Intellectual Property Cores 3.1.4. Planning for Standard Interfaces 3.1.5. Planning for Device Programming 3.1.6. Planning for Device Power Consumption 3.1.7. Planning for Interface I/O Pins 3.1.8. Planning for other EDA Tools 3.1.9. Planning for On-Chip Debugging Tools 3.1.10. Planning HDL Coding Styles
3.1.2. Planning for the Target Device or Board x
3.1.2.1. Device Migration Planning
3.1.8. Planning for other EDA Tools x
3.1.8.1. Third-Party Synthesis Tools 3.1.8.2. Third-Party Simulation Tools
3.1.10. Planning HDL Coding Styles x
3.1.10.1. Design Recommendations 3.1.10.2. Recommended HDL Coding Styles 3.1.10.3. Managing Metastability
3.2. Selecting the Design Methodology x
3.2.1. Flat Design Vs. Incremental Block-based Design 3.2.2. Partial Reconfiguration Design
4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project x
4.1. Creating a New FPGA Design Project 4.2. Migrating Projects from Other Intel® Quartus® Prime Editions to Intel® Quartus® Prime Pro Edition 4.3. Migrating Your AMD* Vivado* Project to Intel® Quartus® Prime Pro Edition 4.4. Migrating Projects Across Operating Systems 4.5. Migrating Project From One Device to Another 4.6. Related Trainings
4.1. Creating a New FPGA Design Project x
4.1.1. Using the Board-Aware Flow 4.1.2. Project Path Length Considerations
4.1.1. Using the Board-Aware Flow x
4.1.1.1. Creating a New Project from a Design Example 4.1.1.2. Specifying a Target Board for the Project
4.1.1.1. Creating a New Project from a Design Example x
4.1.1.1.1. Family, Device & Board Settings 4.1.1.1.2. Accessing Pre-Installed Design Examples 4.1.1.1.3. Accessing Online Design Examples 4.1.1.1.4. Accessing Downloaded Design Examples
4.1.1.1.3. Accessing Online Design Examples x
4.1.1.1.3.1. Internet Connectivity Options 4.1.1.1.3.2. Design Examples Options
4.2. Migrating Projects from Other Intel® Quartus® Prime Editions to Intel® Quartus® Prime Pro Edition x
4.2.1. Keeping Pro Edition Project Files Separate 4.2.2. Upgrading Project Assignments and Constraints 4.2.3. Upgrading IP Cores and Platform Designer Systems 4.2.4. Upgrading Non-Compliant Design RTL
4.2.2. Upgrading Project Assignments and Constraints x
4.2.2.1. Modifying Entity Name Assignments 4.2.2.2. Resolving Timing Constraint Entity Names 4.2.2.3. Verifying Generated Node Name Assignments 4.2.2.4. Replace Logic Lock (Standard) Regions 4.2.2.5. Modifying Signal Tap Logic Analyzer Files 4.2.2.6. Removing References to .qip Files 4.2.2.7. Removing Unsupported Feature Assignments
4.2.2.4. Replace Logic Lock (Standard) Regions x
4.2.2.4.1. Logic Lock Region Assignment Examples
4.2.4. Upgrading Non-Compliant Design RTL x
4.2.4.1. Verifying Verilog Compilation Unit 4.2.4.2. Updating Entity Auto-Discovery 4.2.4.3. Ensuring Distinct VHDL Namespace for Each Library 4.2.4.4. Removing Unsupported Parameter Passing 4.2.4.5. Removing Unsized Constant from WYSIWYG Instantiation 4.2.4.6. Removing Non-Standard Pragmas 4.2.4.7. Declaring Objects Before Initial Values 4.2.4.8. Confining SystemVerilog Features to SystemVerilog Files 4.2.4.9. Avoiding Assignment Mixing in Always Blocks 4.2.4.10. Avoiding Unconnected, Non-Existent Ports 4.2.4.11. Avoiding Invalid Parameter Ranges 4.2.4.12. Updating Verilog HDL and VHDL Type Mapping 4.2.4.13. Converting Symbolic BDF Files to Acceptable File Formats
4.2.4.1. Verifying Verilog Compilation Unit x
4.2.4.1.1. Verilog HDL Configuration Instantiation
4.4. Migrating Projects Across Operating Systems x
4.4.1. Migrating Design Files and Libraries 4.4.2. Design Library Migration Guidelines
4.4.1. Migrating Design Files and Libraries x
4.4.1.1. Use Relative Paths
5. Working With Intel® FPGA IP Cores x
5.1. IP Catalog and Parameter Editor 5.2. Installing and Licensing Intel® FPGA IP Cores 5.3. IP General Settings 5.4. Adding IP to IP Catalog 5.5. Best Practices for Intel® FPGA IP 5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.8. Scripting IP Core Generation 5.9. Modifying an IP Variation 5.10. Upgrading IP Cores 5.11. Simulating Intel® FPGA IP Cores 5.12. Generating Simulation Files for Platform Designer Systems and IP Variants 5.13. Synthesizing IP Cores in Other EDA Tools 5.14. Instantiating IP Cores in HDL 5.15. Support for the IEEE 1735 Encryption Standard 5.16. Related Trainings and Resources
5.1. IP Catalog and Parameter Editor x
5.1.1. The Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
5.2.1. Intel® FPGA IP Evaluation Mode x
5.2.1.1. Intel FPGA IP Versioning 5.2.1.2. Checking the IP License Status
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
5.6.1. Applying Preset Parameters for Specific Applications 5.6.2. Customizing IP Presets
5.6.1. Applying Preset Parameters for Specific Applications x
5.6.1.1. Viewing, Applying, and Deleting IP Presets
5.6.2. Customizing IP Presets x
5.6.2.1. Defining Preset Pin Assignments
5.6.2.1. Defining Preset Pin Assignments x
5.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 5.6.2.1.2. Defining Preset Pin Assignments in a Pin File
5.10. Upgrading IP Cores x
5.10.1. Upgrading IP Cores at Command-Line 5.10.2. Migrating IP Cores to a Different Device 5.10.3. Troubleshooting IP or Platform Designer System Upgrade
5.11. Simulating Intel® FPGA IP Cores x
5.11.1. Generating IP Simulation Files 5.11.2. Scripting IP Simulation
5.11.2. Scripting IP Simulation x
5.11.2.1. Generating a Combined Simulator Setup Script
5.14. Instantiating IP Cores in HDL x
5.14.1. Example Top-Level Verilog HDL Module 5.14.2. Example Top-Level VHDL Module
6. Managing Intel® Quartus® Prime Projects x
6.1. Viewing Basic Project Information 6.2. Exploring Intel® Quartus® Prime Project Contents 6.3. Managing Project Settings 6.4. Viewing Parameter Settings From the Project Navigator 6.5. Managing Logic Design Files 6.6. Managing Timing Constraints 6.7. Integrating Other EDA Tools 6.8. Exporting Compilation Results 6.9. Archiving Projects 6.10. Command-Line Interface 6.11. Related Trainings
6.1. Viewing Basic Project Information x
6.1.1. Using the Compilation Dashboard 6.1.2. Viewing Project Reports 6.1.3. Viewing Project Messages
6.1.3. Viewing Project Messages x
6.1.3.1. Viewing Synthesis Warning Messages 6.1.3.2. Suppressing Message Display 6.1.3.3. Promoting Critical Warnings to Errors
6.2. Exploring Intel® Quartus® Prime Project Contents x
6.2.1. Project File Best Practices
6.5. Managing Logic Design Files x
6.5.1. Including Design Libraries 6.5.2. Creating a Project Copy
6.8. Exporting Compilation Results x
6.8.1. Exporting a Version-Compatible Compilation Database 6.8.2. Importing a Version-Compatible Compilation Database 6.8.3. Creating a Design Partition 6.8.4. Exporting a Design Partition 6.8.5. Reusing a Design Partition 6.8.6. Viewing Quartus Database File Information 6.8.7. Clearing Compilation Results
6.8.6. Viewing Quartus Database File Information x
6.8.6.1. QDB File Attribute Types
6.9. Archiving Projects x
6.9.1. Manually Adding Files To Archives 6.9.2. Archiving Projects for Service Requests 6.9.3. Archiving Projects for External Revision Control 6.9.4. Creating Database-Only Archives
6.9.3. Archiving Projects for External Revision Control x
6.9.3.1. Project Files to Include In External Revision Control
6.10. Command-Line Interface x
6.10.1. Project Revision Commands 6.10.2. Project Archive Commands 6.10.3. Project Database Commands
6.10.3. Project Database Commands x
6.10.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
A. Next Steps After Getting Started x
A.1. Additional Resources A.2. Training
B. Using the Design Space Explorer II x
B.1. Optimizing Project Settings B.2. Running DSE II B.3. Setting Up Remote Farm Using Design Space Explorer II
B.1. Optimizing Project Settings x
B.1.1. Optimizing Settings with Design Space Explorer II B.1.2. Optimizing Settings with Project Revisions B.1.3. Back-Annotating Optimized Assignments
B.1.1. Optimizing Settings with Design Space Explorer II x
B.1.1.1. DSE II Computing Resources B.1.1.2. DSE II Optimization Parameters B.1.1.3. DSE II Result Management
1. Answers to Top FAQs
2. Introduction to Intel® Quartus® Prime Pro Edition
3. Planning FPGA Design for RTL Flow
4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project
5. Working With Intel® FPGA IP Cores
6. Managing Intel® Quartus® Prime Projects
A. Next Steps After Getting Started
B. Using the Design Space Explorer II
C. Document Revision History for Intel® Quartus® Prime Pro Edition User Guide Getting Started
D. Intel® Quartus® Prime Pro Edition User Guides

5.10. Upgrading IP Cores

Any Intel® FPGA IP variations that you generate from a previous version or different edition of the Intel® Quartus® Prime software, may require upgrade before compilation in the current software edition or version. The Project Navigator displays a banner indicating the IP upgrade status. Click Launch IP Upgrade Tool or Project > Upgrade IP Components to upgrade outdated IP cores.
Figure 40. IP Upgrade Alert in Project Navigator


Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, or unsupported for an IP variation in the project. Upgrade IP variations that require upgrade before compilation in the current version of the Intel® Quartus® Prime software.

Note: Upgrading IP cores may append a unique identifier to the original IP core entity names, without similarly modifying the IP instance name. There is no requirement to update these entity references in any supporting Intel® Quartus® Prime file, such as the Intel® Quartus® Prime Settings File (.qsf), Synopsys* Design Constraints File (.sdc), or Signal Tap File (.stp), if these files contain instance names. The Intel® Quartus® Prime software reads only the instance name and ignores the entity name in paths that specify both names. Use only instance names in assignments.
Table 25.  IP Core Upgrade Status
IP Core Status Description
IP Upgraded

Indicates that your IP variation uses the latest version of the Intel® FPGA IP core.
IP Component Outdated

Indicates that your IP variation uses an outdated version of the IP core.
IP End of Life

Indicates that Intel designates the IP core as end-of-life status. You may or may not be able to edit the IP core in the parameter editor. Support for this IP core discontinues in future releases of the Intel® Quartus® Prime software.
IP Upgrade Mismatch Warning

Provides warning of non-critical IP core differences in migrating IP to another device family.
IP has incompatible subcores

 Indicates that the current version of the Intel® Quartus® Prime software does not support compilation of your IP variation, because the IP has incompatible subcores.
Compilation of IP Not Supported

Indicates that the current version of the Intel® Quartus® Prime software does not support compilation of your IP variation. This can occur if another edition of the Intel® Quartus® Prime software, such as the Intel® Quartus® Prime Standard Edition, generated this IP. Replace this IP component with a compatible component in the current edition.
Note: Beginning with the Intel® Quartus® Prime Pro Edition software version 19.1, IP upgrade supports migration of IP released within one year of the Intel® Quartus® Prime Pro Edition software version, as the following chart defines:
Figure 41.  Intel® Quartus® Prime Pro Edition IP Version Upgrade Paths


Follow these steps to upgrade IP cores:

  1. In the latest version of the Intel® Quartus® Prime software, open the Intel® Quartus® Prime project containing an outdated IP core variation. The Upgrade IP Components dialog box automatically displays the status of IP cores in your project, along with instructions for upgrading each core. To access this dialog box manually, click Project > Upgrade IP Components.
  2. To upgrade one or more IP cores that support automatic upgrade, ensure that you turn on the Auto Upgrade option for the IP cores, and click Auto Upgrade. The Status and Version columns update when upgrade is complete. Example designs that any Intel® FPGA IP core provides regenerate automatically whenever you upgrade an IP core.
  3. To manually upgrade an individual IP core, select the IP core and click Upgrade in Editor (or simply double-click the IP core name). The parameter editor opens, allowing you to adjust parameters and regenerate the latest version of the IP core.
    Figure 42. Upgrading IP Cores ( Intel® Quartus® Prime Pro Edition Example)


    Note: Intel® FPGA IP cores older than Intel® Quartus® Prime software version 12.0 do not support upgrade. Intel verifies that the current version of the Intel® Quartus® Prime software compiles the previous two versions of each IP core. The Intel® FPGA IP Core Release Notes reports any verification exceptions for Intel® FPGA IP cores. Intel does not verify compilation for IP cores older than the previous two releases.

Section Content
Upgrading IP Cores at Command-Line
Migrating IP Cores to a Different Device
Troubleshooting IP or Platform Designer System Upgrade

Related Information
Level Two Title