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3.2.2. Partial Reconfiguration Design
Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. You can define multiple personas for a particular region in your design without impacting operation in areas outside this region. This methodology is effective in systems with various functions that time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems.
The Intel® Quartus® Prime Pro Edition software supports the PR feature for the Intel Agilex® 7, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX device families.
PR provides the following advantages over a flat design:
- Allows run-time design reconfiguration.
- Increases scalability of the design through time-multiplexing.
- Lowers cost and power consumption through efficient use of board space.
- Supports dynamic time-multiplexing functions in the design.
- Improves initial programming time through smaller bitstreams.
- Reduces system downtime through line upgrades.
- Enables easy system updates by allowing remote hardware change.
- Supports a simplified compilation flow for partial reconfiguration.
For more information about the PR design, refer to the Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.