Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Introduction to Intel® Quartus® Prime Pro Edition 3. Planning FPGA Design for RTL Flow 4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project 5. Working With Intel® FPGA IP Cores 6. Managing Intel® Quartus® Prime Projects A. Next Steps After Getting Started B. Using the Design Space Explorer II C. Document Revision History for Intel® Quartus® Prime Pro Edition User Guide Getting Started D. Intel® Quartus® Prime Pro Edition User Guides
2. Introduction to Intel® Quartus® Prime Pro Edition x
2.1. Before You Begin
2.1. Before You Begin x
2.1.1. Prerequisite Knowledge and Training 2.1.2. Navigate Content Through Tasks 2.1.3. Acronyms
3. Planning FPGA Design for RTL Flow x
3.1. Design Planning 3.2. Selecting the Design Methodology 3.3. Related Trainings
3.1. Design Planning x
3.1.1. Creating a Design Specification and Test Plan 3.1.2. Planning for the Target Device or Board 3.1.3. Planning for Intellectual Property Cores 3.1.4. Planning for Standard Interfaces 3.1.5. Planning for Device Programming 3.1.6. Planning for Device Power Consumption 3.1.7. Planning for Interface I/O Pins 3.1.8. Planning for other EDA Tools 3.1.9. Planning for On-Chip Debugging Tools 3.1.10. Planning HDL Coding Styles
3.1.2. Planning for the Target Device or Board x
3.1.2.1. Device Migration Planning
3.1.8. Planning for other EDA Tools x
3.1.8.1. Third-Party Synthesis Tools 3.1.8.2. Third-Party Simulation Tools
3.1.10. Planning HDL Coding Styles x
3.1.10.1. Design Recommendations 3.1.10.2. Recommended HDL Coding Styles 3.1.10.3. Managing Metastability
3.2. Selecting the Design Methodology x
3.2.1. Flat Design Vs. Incremental Block-based Design 3.2.2. Partial Reconfiguration Design
4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project x
4.1. Creating a New FPGA Design Project 4.2. Migrating Projects from Other Intel® Quartus® Prime Editions to Intel® Quartus® Prime Pro Edition 4.3. Migrating Your AMD* Vivado* Project to Intel® Quartus® Prime Pro Edition 4.4. Migrating Projects Across Operating Systems 4.5. Migrating Project From One Device to Another 4.6. Related Trainings
4.1. Creating a New FPGA Design Project x
4.1.1. Using the Board-Aware Flow 4.1.2. Project Path Length Considerations
4.1.1. Using the Board-Aware Flow x
4.1.1.1. Creating a New Project from a Design Example 4.1.1.2. Specifying a Target Board for the Project
4.1.1.1. Creating a New Project from a Design Example x
4.1.1.1.1. Family, Device & Board Settings 4.1.1.1.2. Accessing Pre-Installed Design Examples 4.1.1.1.3. Accessing Online Design Examples 4.1.1.1.4. Accessing Downloaded Design Examples
4.1.1.1.3. Accessing Online Design Examples x
4.1.1.1.3.1. Internet Connectivity Options 4.1.1.1.3.2. Design Examples Options
4.2. Migrating Projects from Other Intel® Quartus® Prime Editions to Intel® Quartus® Prime Pro Edition x
4.2.1. Keeping Pro Edition Project Files Separate 4.2.2. Upgrading Project Assignments and Constraints 4.2.3. Upgrading IP Cores and Platform Designer Systems 4.2.4. Upgrading Non-Compliant Design RTL
4.2.2. Upgrading Project Assignments and Constraints x
4.2.2.1. Modifying Entity Name Assignments 4.2.2.2. Resolving Timing Constraint Entity Names 4.2.2.3. Verifying Generated Node Name Assignments 4.2.2.4. Replace Logic Lock (Standard) Regions 4.2.2.5. Modifying Signal Tap Logic Analyzer Files 4.2.2.6. Removing References to .qip Files 4.2.2.7. Removing Unsupported Feature Assignments
4.2.2.4. Replace Logic Lock (Standard) Regions x
4.2.2.4.1. Logic Lock Region Assignment Examples
4.2.4. Upgrading Non-Compliant Design RTL x
4.2.4.1. Verifying Verilog Compilation Unit 4.2.4.2. Updating Entity Auto-Discovery 4.2.4.3. Ensuring Distinct VHDL Namespace for Each Library 4.2.4.4. Removing Unsupported Parameter Passing 4.2.4.5. Removing Unsized Constant from WYSIWYG Instantiation 4.2.4.6. Removing Non-Standard Pragmas 4.2.4.7. Declaring Objects Before Initial Values 4.2.4.8. Confining SystemVerilog Features to SystemVerilog Files 4.2.4.9. Avoiding Assignment Mixing in Always Blocks 4.2.4.10. Avoiding Unconnected, Non-Existent Ports 4.2.4.11. Avoiding Invalid Parameter Ranges 4.2.4.12. Updating Verilog HDL and VHDL Type Mapping 4.2.4.13. Converting Symbolic BDF Files to Acceptable File Formats
4.2.4.1. Verifying Verilog Compilation Unit x
4.2.4.1.1. Verilog HDL Configuration Instantiation
4.4. Migrating Projects Across Operating Systems x
4.4.1. Migrating Design Files and Libraries 4.4.2. Design Library Migration Guidelines
4.4.1. Migrating Design Files and Libraries x
4.4.1.1. Use Relative Paths
5. Working With Intel® FPGA IP Cores x
5.1. IP Catalog and Parameter Editor 5.2. Installing and Licensing Intel® FPGA IP Cores 5.3. IP General Settings 5.4. Adding IP to IP Catalog 5.5. Best Practices for Intel® FPGA IP 5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.8. Scripting IP Core Generation 5.9. Modifying an IP Variation 5.10. Upgrading IP Cores 5.11. Simulating Intel® FPGA IP Cores 5.12. Generating Simulation Files for Platform Designer Systems and IP Variants 5.13. Synthesizing IP Cores in Other EDA Tools 5.14. Instantiating IP Cores in HDL 5.15. Support for the IEEE 1735 Encryption Standard 5.16. Related Trainings and Resources
5.1. IP Catalog and Parameter Editor x
5.1.1. The Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
5.2.1. Intel® FPGA IP Evaluation Mode x
5.2.1.1. Intel FPGA IP Versioning 5.2.1.2. Checking the IP License Status
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
5.6.1. Applying Preset Parameters for Specific Applications 5.6.2. Customizing IP Presets
5.6.1. Applying Preset Parameters for Specific Applications x
5.6.1.1. Viewing, Applying, and Deleting IP Presets
5.6.2. Customizing IP Presets x
5.6.2.1. Defining Preset Pin Assignments
5.6.2.1. Defining Preset Pin Assignments x
5.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 5.6.2.1.2. Defining Preset Pin Assignments in a Pin File
5.10. Upgrading IP Cores x
5.10.1. Upgrading IP Cores at Command-Line 5.10.2. Migrating IP Cores to a Different Device 5.10.3. Troubleshooting IP or Platform Designer System Upgrade
5.11. Simulating Intel® FPGA IP Cores x
5.11.1. Generating IP Simulation Files 5.11.2. Scripting IP Simulation
5.11.2. Scripting IP Simulation x
5.11.2.1. Generating a Combined Simulator Setup Script
5.14. Instantiating IP Cores in HDL x
5.14.1. Example Top-Level Verilog HDL Module 5.14.2. Example Top-Level VHDL Module
6. Managing Intel® Quartus® Prime Projects x
6.1. Viewing Basic Project Information 6.2. Exploring Intel® Quartus® Prime Project Contents 6.3. Managing Project Settings 6.4. Viewing Parameter Settings From the Project Navigator 6.5. Managing Logic Design Files 6.6. Managing Timing Constraints 6.7. Integrating Other EDA Tools 6.8. Exporting Compilation Results 6.9. Archiving Projects 6.10. Command-Line Interface 6.11. Related Trainings
6.1. Viewing Basic Project Information x
6.1.1. Using the Compilation Dashboard 6.1.2. Viewing Project Reports 6.1.3. Viewing Project Messages
6.1.3. Viewing Project Messages x
6.1.3.1. Viewing Synthesis Warning Messages 6.1.3.2. Suppressing Message Display 6.1.3.3. Promoting Critical Warnings to Errors
6.2. Exploring Intel® Quartus® Prime Project Contents x
6.2.1. Project File Best Practices
6.5. Managing Logic Design Files x
6.5.1. Including Design Libraries 6.5.2. Creating a Project Copy
6.8. Exporting Compilation Results x
6.8.1. Exporting a Version-Compatible Compilation Database 6.8.2. Importing a Version-Compatible Compilation Database 6.8.3. Creating a Design Partition 6.8.4. Exporting a Design Partition 6.8.5. Reusing a Design Partition 6.8.6. Viewing Quartus Database File Information 6.8.7. Clearing Compilation Results
6.8.6. Viewing Quartus Database File Information x
6.8.6.1. QDB File Attribute Types
6.9. Archiving Projects x
6.9.1. Manually Adding Files To Archives 6.9.2. Archiving Projects for Service Requests 6.9.3. Archiving Projects for External Revision Control 6.9.4. Creating Database-Only Archives
6.9.3. Archiving Projects for External Revision Control x
6.9.3.1. Project Files to Include In External Revision Control
6.10. Command-Line Interface x
6.10.1. Project Revision Commands 6.10.2. Project Archive Commands 6.10.3. Project Database Commands
6.10.3. Project Database Commands x
6.10.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
A. Next Steps After Getting Started x
A.1. Additional Resources A.2. Training
B. Using the Design Space Explorer II x
B.1. Optimizing Project Settings B.2. Running DSE II B.3. Setting Up Remote Farm Using Design Space Explorer II
B.1. Optimizing Project Settings x
B.1.1. Optimizing Settings with Design Space Explorer II B.1.2. Optimizing Settings with Project Revisions B.1.3. Back-Annotating Optimized Assignments
B.1.1. Optimizing Settings with Design Space Explorer II x
B.1.1.1. DSE II Computing Resources B.1.1.2. DSE II Optimization Parameters B.1.1.3. DSE II Result Management
1. Answers to Top FAQs
2. Introduction to Intel® Quartus® Prime Pro Edition
3. Planning FPGA Design for RTL Flow
4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project
5. Working With Intel® FPGA IP Cores
6. Managing Intel® Quartus® Prime Projects
A. Next Steps After Getting Started
B. Using the Design Space Explorer II
C. Document Revision History for Intel® Quartus® Prime Pro Edition User Guide Getting Started
D. Intel® Quartus® Prime Pro Edition User Guides

3.1.7. Planning for Interface I/O Pins

In many design environments, FPGA designers want to plan the top-level FPGA I/O pins early to help board designers begin the PCB design and layout. The I/O capabilities and board layout guidelines of the FPGA device influence pin locations and other types of assignments. If the board design team specifies an FPGA pin-out, the pin locations must be verified in the FPGA placement and routing software to avoid board design changes.

You can create a preliminary pin-out for an Intel FPGA with the Intel® Quartus® Prime Pin Planner before you develop the source code, based on standard I/O interfaces (such as memory and bus interfaces) and any other I/O requirements for your system.

Figure 8. Pin Planner

The Intel® Quartus® Prime I/O Assignment Analysis checks that the pin locations and assignments are supported in the target FPGA architecture. You can then use I/O Assignment Analysis to validate I/O-related assignments that you create or modify throughout the design process. When you compile your design in the Intel® Quartus® Prime software, I/O Assignment Analysis runs automatically in the Fitter to validate that the assignments meet all the device requirements and generates error messages.

Early in the design process, before creating the source code, the system architect has information about the standard I/O interfaces (such as memory and bus interfaces), the IP cores in your design, and any other I/O-related assignments defined by system requirements. You can use this information with the Early Pin Planning feature in the Pin Planner to specify details about the design I/O interfaces. You can then create a top-level design file that includes all I/O information.

The Pin Planner interfaces with the IP core parameter editor, which allows you to create or import custom IP cores that use I/O interfaces. You can configure how to connect the functions and cores to each other by specifying matching node names for selected ports. You can create other I/O-related assignments for these interfaces or other design I/O pins in the Pin Planner, as described in this section. The Pin Planner creates virtual pin assignments for internal nodes, so internal nodes are not assigned to device pins during compilation.

You can use the I/O analysis results to change pin assignments or IP parameters even before you create your design, and repeat the checking process until the I/O interface meets your design requirements and passes the pin checks in the Intel® Quartus® Prime software. When you complete initial pin planning, you can create a revision based on the Intel® Quartus® Prime-generated netlist. You can then use the generated netlist to develop the top-level design file for your design, or disregard the generated netlist and use the generated Intel® Quartus® Prime Settings File (.qsf) with your design.

During this early pin planning, after you have generated a top-level design file, or when you have developed your design source code, you can assign pin locations and assignments with the Pin Planner.

With the Pin Planner, you can identify I/O banks, voltage reference (VREF) groups, and differential pin pairings to help you through the I/O planning process. If you selected a migration device, the Pin Migration View highlights the pins that have changed functions in the migration device when compared to the currently selected device. Selecting the pins in the Device Migration view cross-probes to the rest of the Pin Planner, so that you can use device migration information when planning your pin assignments. You can also configure board trace models of selected pins for use in “board-aware” signal integrity reports generated with the Enable Advanced I/O Timing option . This option ensures that you get accurate I/O timing analysis. You can use a Microsoft Excel spreadsheet to start the I/O planning process if you normally use a spreadsheet in your design flow, and you can export a Comma-Separated Value File (.csv) containing your I/O assignments for spreadsheet use when you assign all pins.

When you complete your pin planning, you can pass pin location information to PCB designers. The Pin Planner is tightly integrated with certain PCB design EDA tools, and can read pin location changes from these tools to check suggested changes. Your pin assignments must match between the Intel® Quartus® Prime software and your schematic and board layout tools to ensure the FPGA works correctly on the board, especially if you must make changes to the pin-out. The system architect uses the Intel® Quartus® Prime software to pass pin information to team members designing individual logic blocks, allowing them to achieve better timing closure when they compile their design.

Start FPGA planning before you complete the HDL for your design to improve the confidence in early board layouts, reduce the chance of error, and improve the overall time to market of the design. When you complete your design, use the Fitter reports for the final sign-off of pin assignments. After compilation, the Intel® Quartus® Prime software generates the Pin-Out File (.pin), and you can use this file to verify that each pin is correctly connected in board schematics.

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