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Ixiasoft
3. Planning FPGA Design for RTL Flow
Navigating Content Through Tasks
Use the following table to navigate this guide through user-tasks:
Planning for RTL flow is an essential step for advanced FPGA design. This chapter provides some useful tips and programming methods to consider in your planning process to help you detect and solve potential problems early in the design cycle. Determining your design priorities early on helps you to choose the best device, tools, features, and methodologies for your design.
Review the following topics to help you get started with the planning process: