Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Introduction to Intel® Quartus® Prime Pro Edition 3. Planning FPGA Design for RTL Flow 4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project 5. Working With Intel® FPGA IP Cores 6. Managing Intel® Quartus® Prime Projects A. Next Steps After Getting Started B. Using the Design Space Explorer II C. Document Revision History for Intel® Quartus® Prime Pro Edition User Guide Getting Started D. Intel® Quartus® Prime Pro Edition User Guides
2. Introduction to Intel® Quartus® Prime Pro Edition x
Intel® Quartus® Prime Pro Edition Software Quick Start Steps Intel® Quartus® Prime Software Editions Supported Features Supported Intel FPGA Developmental Tools 2.1. Before You Begin
2.1. Before You Begin x
2.1.1. Prerequisite Knowledge and Training 2.1.2. Navigate Content Through Tasks 2.1.3. Acronyms
3. Planning FPGA Design for RTL Flow x
3.1. Design Planning 3.2. Selecting the Design Methodology 3.3. Related Trainings
3.1. Design Planning x
3.1.1. Creating a Design Specification and Test Plan 3.1.2. Planning for the Target Device or Board 3.1.3. Planning for Intellectual Property Cores 3.1.4. Planning for Standard Interfaces 3.1.5. Planning for Device Programming 3.1.6. Planning for Device Power Consumption 3.1.7. Planning for Interface I/O Pins 3.1.8. Planning for other EDA Tools 3.1.9. Planning for On-Chip Debugging Tools 3.1.10. Planning HDL Coding Styles
3.1.2. Planning for the Target Device or Board x
3.1.2.1. Device Migration Planning
3.1.8. Planning for other EDA Tools x
3.1.8.1. Third-Party Synthesis Tools 3.1.8.2. Third-Party Simulation Tools
3.1.10. Planning HDL Coding Styles x
3.1.10.1. Design Recommendations 3.1.10.2. Recommended HDL Coding Styles 3.1.10.3. Managing Metastability
3.2. Selecting the Design Methodology x
3.2.1. Flat Design Vs. Incremental Block-based Design 3.2.2. Partial Reconfiguration Design
4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project x
4.1. Creating a New FPGA Design Project 4.2. Migrating Projects from Other Intel® Quartus® Prime Editions to Intel® Quartus® Prime Pro Edition 4.3. Migrating Your AMD* Vivado* Project to Intel® Quartus® Prime Pro Edition 4.4. Migrating Projects Across Operating Systems 4.5. Migrating Project From One Device to Another 4.6. Related Trainings
4.1. Creating a New FPGA Design Project x
4.1.1. Using the Board-Aware Flow 4.1.2. Project Path Length Considerations
4.1.1. Using the Board-Aware Flow x
4.1.1.1. Creating a New Project from a Design Example 4.1.1.2. Specifying a Target Board for the Project
4.1.1.1. Creating a New Project from a Design Example x
4.1.1.1.1. Family, Device & Board Settings 4.1.1.1.2. Accessing Pre-Installed Design Examples 4.1.1.1.3. Accessing Online Design Examples 4.1.1.1.4. Accessing Downloaded Design Examples
4.1.1.1.3. Accessing Online Design Examples x
4.1.1.1.3.1. Internet Connectivity Options 4.1.1.1.3.2. Design Examples Options
4.2. Migrating Projects from Other Intel® Quartus® Prime Editions to Intel® Quartus® Prime Pro Edition x
4.2.1. Keeping Pro Edition Project Files Separate 4.2.2. Upgrading Project Assignments and Constraints 4.2.3. Upgrading IP Cores and Platform Designer Systems 4.2.4. Upgrading Non-Compliant Design RTL
4.2.2. Upgrading Project Assignments and Constraints x
4.2.2.1. Modifying Entity Name Assignments 4.2.2.2. Resolving Timing Constraint Entity Names 4.2.2.3. Verifying Generated Node Name Assignments 4.2.2.4. Replace Logic Lock (Standard) Regions 4.2.2.5. Modifying Signal Tap Logic Analyzer Files 4.2.2.6. Removing References to .qip Files 4.2.2.7. Removing Unsupported Feature Assignments
4.2.2.4. Replace Logic Lock (Standard) Regions x
4.2.2.4.1. Logic Lock Region Assignment Examples
4.2.4. Upgrading Non-Compliant Design RTL x
4.2.4.1. Verifying Verilog Compilation Unit 4.2.4.2. Updating Entity Auto-Discovery 4.2.4.3. Ensuring Distinct VHDL Namespace for Each Library 4.2.4.4. Removing Unsupported Parameter Passing 4.2.4.5. Removing Unsized Constant from WYSIWYG Instantiation 4.2.4.6. Removing Non-Standard Pragmas 4.2.4.7. Declaring Objects Before Initial Values 4.2.4.8. Confining SystemVerilog Features to SystemVerilog Files 4.2.4.9. Avoiding Assignment Mixing in Always Blocks 4.2.4.10. Avoiding Unconnected, Non-Existent Ports 4.2.4.11. Avoiding Invalid Parameter Ranges 4.2.4.12. Updating Verilog HDL and VHDL Type Mapping 4.2.4.13. Converting Symbolic BDF Files to Acceptable File Formats
4.2.4.1. Verifying Verilog Compilation Unit x
4.2.4.1.1. Verilog HDL Configuration Instantiation
4.4. Migrating Projects Across Operating Systems x
4.4.1. Migrating Design Files and Libraries 4.4.2. Design Library Migration Guidelines
4.4.1. Migrating Design Files and Libraries x
4.4.1.1. Use Relative Paths
5. Working With Intel® FPGA IP Cores x
5.1. IP Catalog and Parameter Editor 5.2. Installing and Licensing Intel® FPGA IP Cores 5.3. IP General Settings 5.4. Adding IP to IP Catalog 5.5. Best Practices for Intel® FPGA IP 5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.8. Scripting IP Core Generation 5.9. Modifying an IP Variation 5.10. Upgrading IP Cores 5.11. Simulating Intel® FPGA IP Cores 5.12. Generating Simulation Files for Platform Designer Systems and IP Variants 5.13. Synthesizing IP Cores in Other EDA Tools 5.14. Instantiating IP Cores in HDL 5.15. Support for the IEEE 1735 Encryption Standard 5.16. Related Trainings and Resources
5.1. IP Catalog and Parameter Editor x
5.1.1. The Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
5.2.1. Intel® FPGA IP Evaluation Mode x
5.2.1.1. Intel FPGA IP Versioning 5.2.1.2. Checking the IP License Status
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
5.6.1. Applying Preset Parameters for Specific Applications 5.6.2. Customizing IP Presets
5.6.1. Applying Preset Parameters for Specific Applications x
5.6.1.1. Viewing, Applying, and Deleting IP Presets
5.6.2. Customizing IP Presets x
5.6.2.1. Defining Preset Pin Assignments
5.6.2.1. Defining Preset Pin Assignments x
5.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 5.6.2.1.2. Defining Preset Pin Assignments in a Pin File
5.10. Upgrading IP Cores x
5.10.1. Upgrading IP Cores at Command-Line 5.10.2. Migrating IP Cores to a Different Device 5.10.3. Troubleshooting IP or Platform Designer System Upgrade
5.11. Simulating Intel® FPGA IP Cores x
5.11.1. Generating IP Simulation Files 5.11.2. Scripting IP Simulation
5.11.2. Scripting IP Simulation x
5.11.2.1. Generating a Combined Simulator Setup Script
5.14. Instantiating IP Cores in HDL x
5.14.1. Example Top-Level Verilog HDL Module 5.14.2. Example Top-Level VHDL Module
6. Managing Intel® Quartus® Prime Projects x
6.1. Viewing Basic Project Information 6.2. Exploring Intel® Quartus® Prime Project Contents 6.3. Managing Project Settings 6.4. Viewing Parameter Settings From the Project Navigator 6.5. Managing Logic Design Files 6.6. Managing Timing Constraints 6.7. Integrating Other EDA Tools 6.8. Exporting Compilation Results 6.9. Archiving Projects 6.10. Command-Line Interface 6.11. Related Trainings
6.1. Viewing Basic Project Information x
6.1.1. Using the Compilation Dashboard 6.1.2. Viewing Project Reports 6.1.3. Viewing Project Messages
6.1.3. Viewing Project Messages x
6.1.3.1. Viewing Synthesis Warning Messages 6.1.3.2. Suppressing Message Display 6.1.3.3. Promoting Critical Warnings to Errors
6.2. Exploring Intel® Quartus® Prime Project Contents x
6.2.1. Project File Best Practices
6.5. Managing Logic Design Files x
6.5.1. Including Design Libraries 6.5.2. Creating a Project Copy
6.8. Exporting Compilation Results x
6.8.1. Exporting a Version-Compatible Compilation Database 6.8.2. Importing a Version-Compatible Compilation Database 6.8.3. Creating a Design Partition 6.8.4. Exporting a Design Partition 6.8.5. Reusing a Design Partition 6.8.6. Viewing Quartus Database File Information 6.8.7. Clearing Compilation Results
6.8.6. Viewing Quartus Database File Information x
6.8.6.1. QDB File Attribute Types
6.9. Archiving Projects x
6.9.1. Manually Adding Files To Archives 6.9.2. Archiving Projects for Service Requests 6.9.3. Archiving Projects for External Revision Control 6.9.4. Creating Database-Only Archives
6.9.3. Archiving Projects for External Revision Control x
6.9.3.1. Project Files to Include In External Revision Control
6.10. Command-Line Interface x
6.10.1. Project Revision Commands 6.10.2. Project Archive Commands 6.10.3. Project Database Commands
6.10.3. Project Database Commands x
6.10.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
A. Next Steps After Getting Started x
A.1. Additional Resources A.2. Training
B. Using the Design Space Explorer II x
B.1. Optimizing Project Settings B.2. Running DSE II B.3. Setting Up Remote Farm Using Design Space Explorer II
B.1. Optimizing Project Settings x
B.1.1. Optimizing Settings with Design Space Explorer II B.1.2. Optimizing Settings with Project Revisions B.1.3. Back-Annotating Optimized Assignments
B.1.1. Optimizing Settings with Design Space Explorer II x
B.1.1.1. DSE II Computing Resources B.1.1.2. DSE II Optimization Parameters B.1.1.3. DSE II Result Management
1. Answers to Top FAQs
2. Introduction to Intel® Quartus® Prime Pro Edition
3. Planning FPGA Design for RTL Flow
4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project
5. Working With Intel® FPGA IP Cores
6. Managing Intel® Quartus® Prime Projects
A. Next Steps After Getting Started
B. Using the Design Space Explorer II
C. Document Revision History for Intel® Quartus® Prime Pro Edition User Guide Getting Started
D. Intel® Quartus® Prime Pro Edition User Guides

2. Introduction to Intel® Quartus® Prime Pro Edition

This user guide describes basic concepts, files, and design flow of the Intel® Quartus® Prime Pro Edition software, including initial design planning considerations, selecting a starting point to set up your Intel® Quartus® Prime Pro Edition project and managing those projects and working with intellectual property (IP).

The Intel® Quartus® Prime design suite is a comprehensive development platform to design with Intel FPGAs1, from design entry and synthesis to optimization, verification, simulation, and binary generation. The Intel® Quartus® Prime software supports fast design processing, straightforward device programming, and integration with other industry-standard EDA tools. The user interface makes it easy for you to focus on your design—not on the design tool. The modular compiler streamlines the FPGA development process and ensures the highest performance for the least effort.

Intel® Quartus® Prime Pro Edition Software Quick Start Steps

Use the following links to get started with the Intel® Quartus® Prime Pro Edition software:

Table 1.   Intel® Quartus® Prime Pro Edition Software Quick Start Steps
Step   Useful Links
Determine the System Requirements Verify hardware and software requirements and review Intel® Quartus® Prime Pro Edition software release notes.
Download the software Download the latest Intel® Quartus® Prime Pro Edition software.
Install the software Install the latest Intel® Quartus® Prime Pro Edition software.
Generate 90-days Fixed-node License Generate 90- days free license in Intel® FPGA Self-Service Licensing Center (SSLC).
Start the software

On Windows:

Use one of the following options:

  • On the desktop, double-click the Intel® FPGA software icon.

  • Click Start > All Programs > Intel FPGA <Version> Pro Edition > Quartus (Quartus Prime Pro <Version>
  • At the command prompt, type:

    <installation-directory>\bin64\quartus

On Linux:

  • At the command prompt, type:

    <installation-directory>/quartus/bin/quartus

Starting the Intel® Quartus® Prime Software
Set up the generated license in the Intel® Quartus® Prime Pro Edition software In the Intel® Quartus® Prime Pro Edition software, click Tools > License Setup, browse and select the license file, and click OK.
Intel® Quartus® Prime Software Home Page Main page of the Intel® Quartus® Prime software.

 

Intel® Quartus® Prime Software Editions

The Intel® Quartus® Prime Software is available in three editions based on your design requirements:

Table 2.   Intel® Quartus® Prime Software Editions
  Pro Edition Standard Edition Lite Edition
Optimized to support the advanced features in Intel FPGAs and SoCs with the following device families:
  • Intel Agilex® 7
  • Intel® Stratix® 10
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
Includes extensive support for earlier device families in addition to the following device families:
  • Intel® Cyclone® 10 LP
  • Intel® MAX® 10
An ideal entry point to Intel’s high-volume device families and is available as a free download with no license file required.

Supported Features

The following is the Intel® Quartus® Prime feature support matrix:

Figure 2.  Intel® Quartus® Prime Feature Support Matrix

The following features are only available in the Intel® Quartus® Prime Pro Edition software:

Table 3.  Supported Features of the Intel® Quartus® Prime Pro Edition Software
Feature Description
Hyper-Aware Design Flow Use Hyper-Retiming to reach the highest performance in Intel Agilex® 7 and Intel® Stratix® 10 devices.
Advanced synthesis Integrates new, stricter language parser supporting all major IEEE RTL languages, with enhanced algorithms, and parallel synthesis capabilities, and support for SystemVerilog 2009.
Hierarchical project structure Preserves individual post-synthesis, post-placement, and post-place and route results for design instances. Optimizes without impacting other partition placement or routing.
Incremental Fitter Optimizations Run and optimize Fitter stages incrementally. Each Fitter stage generates detailed reports.
Faster, more accurate I/O placement Plan interface I/O in Interface Planner.
Platform Designer (Pro) Builds on the system design and custom IP integration capabilities of Platform Designer (Standard). Platform Designer (Pro) introduces hierarchical isolation between system interconnect and IP components.
Block-Based Design Flows Preserve and reuse design blocks at various stages of compilation.

Intel® Quartus® Prime Pro Edition software does not support the following Intel® Quartus® Prime Standard Edition features:

  • I/O Timing Analysis
  • NativeLink third party tool integration (other third-party tool integration available)
  • Video and Image Processing Suite IP Cores
  • Talkback features
  • Various register merging and duplication settings
  • Saving a node-level netlist as .vqm or RTL to schematic conversion

Supported Intel FPGA Developmental Tools

The Intel® Quartus® Prime software suite supports the following Intel FPGA development tools:

Table 4.  Intel FPGA Developmental Tools Supported by the Intel® Quartus® Prime Software Suite
Tools Description
Questa*-Intel® FPGA Edition Simulates FPGA designs using Intel® -specific simulation libraries. It includes all features of Siemens EDA Questa* Core, including behavioral simulation, HDL test benches, and Tcl scripting.
Intel® Advanced Link Analyzer Analyzes jitter/noise and evaluates high-speed serial link performance. It is an ideal predesign tool supporting Intel FPGA IBIS-AMI standards and enhanced models to help you understand how Intel® FPGA solutions can fit your system requirements.
Intel® SoC FPGA Embedded Development Suite A comprehensive tool suite for embedded software development on Intel® SoC FPGAs.
Nios® II Embedded Design Suite (EDS) A comprehensive Nios® II software design development package.
Ashling* RiscFree* IDE for Intel® FPGAs Integrated development environment for creating embedded applications on the RISC-V-based Nios® V soft processors and the Arm*-based hard processor system.
Intel® HLS Compiler A high-level synthesis (HLS) tool that accepts untimed C++ code as an input and generates production-quality register transfer level (RTL) code optimized for Intel® FPGAs. This tool accelerates verification time over RTL by raising the abstraction level for FPGA hardware design. Models developed in C++ have typically verified orders of magnitude faster than RTL.
DSP Builder for Intel® FPGAs Supports a model-based design flow from algorithms to hardware in a common environment.
Intel® oneAPI Base Toolkit Enables you to target FPGAs for heterogeneous acceleration and simulate entire system flows by abstracting some parts of the hardware.
Intel® Simics® simulator for Intel® FPGAs A full-system simulator that supports defining, developing, and deploying virtual platforms.
Intel® FPGA AI Suite Provides several components to help in enabling Artificial Intelligence (AI) and creating optimized Intel FPGA AI platforms efficiently.
Intel® FPGA Power and Thermal Calculator Estimates your design's power consumption and provides thermal design parameters for Intel FPGA devices, such as Intel Agilex® 7 and Intel® Stratix® 10.

Section Content
Before You Begin

1 A field-programmable gate array (FPGA) is a specialized integrated circuit that you can customize and reconfigure multiple times. To learn about and select a target Intel FPGA device family, refer to https://www.intel.com/content/www/us/en/products/details/fpga.html.
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