Visible to Intel only — GUID: jbr1442881388255
Ixiasoft
Visible to Intel only — GUID: jbr1442881388255
Ixiasoft
4.2.3. Upgrading IP Cores and Platform Designer Systems
Other Quartus software products use a proprietary Verilog configuration scheme within the top level of IP cores and Platform Designer systems for synthesis files. The Intel® Quartus® Prime Pro Edition does not support this scheme. To upgrade all IP cores and Platform Designer systems in your project, click Project > Upgrade IP Components.2
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
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IP and Platform Designer system generation use a proprietary Verilog HDL configuration scheme within the top level of IP cores and Platform Designer systems for synthesis files. This proprietary Verilog HDL configuration scheme prevents RTL entities from ambiguous instantiation errors during synthesis. However, these errors may manifest in simulation. Resolving this issue requires writing a Verilog HDL configuration to disambiguate the instantiation, delete the duplicate entity from the project, or rename one of the conflicting entities. Intel® Quartus® Prime Pro Edition IP strategy resolves these issues. | IP and Platform Designer system generation does not use proprietary Verilog HDL configurations. The compilation library scheme changes in the following ways:
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