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1. Answers to Top FAQs
2. Introduction to Intel® Quartus® Prime Pro Edition
3. Planning FPGA Design for RTL Flow
4. Selecting a Starting Point for Your Intel® Quartus® Prime Pro Edition Project
5. Working With Intel® FPGA IP Cores
6. Managing Intel® Quartus® Prime Projects
A. Next Steps After Getting Started
B. Using the Design Space Explorer II
C. Document Revision History for Intel® Quartus® Prime Pro Edition User Guide Getting Started
D. Intel® Quartus® Prime Pro Edition User Guides
3.1.1. Creating a Design Specification and Test Plan
3.1.2. Planning for the Target Device or Board
3.1.3. Planning for Intellectual Property Cores
3.1.4. Planning for Standard Interfaces
3.1.5. Planning for Device Programming
3.1.6. Planning for Device Power Consumption
3.1.7. Planning for Interface I/O Pins
3.1.8. Planning for other EDA Tools
3.1.9. Planning for On-Chip Debugging Tools
3.1.10. Planning HDL Coding Styles
4.1. Creating a New FPGA Design Project
4.2. Migrating Projects from Other Intel® Quartus® Prime Editions to Intel® Quartus® Prime Pro Edition
4.3. Migrating Your AMD* Vivado* Project to Intel® Quartus® Prime Pro Edition
4.4. Migrating Projects Across Operating Systems
4.5. Migrating Project From One Device to Another
4.6. Related Trainings
4.2.2.1. Modifying Entity Name Assignments
4.2.2.2. Resolving Timing Constraint Entity Names
4.2.2.3. Verifying Generated Node Name Assignments
4.2.2.4. Replace Logic Lock (Standard) Regions
4.2.2.5. Modifying Signal Tap Logic Analyzer Files
4.2.2.6. Removing References to .qip Files
4.2.2.7. Removing Unsupported Feature Assignments
4.2.4.1. Verifying Verilog Compilation Unit
4.2.4.2. Updating Entity Auto-Discovery
4.2.4.3. Ensuring Distinct VHDL Namespace for Each Library
4.2.4.4. Removing Unsupported Parameter Passing
4.2.4.5. Removing Unsized Constant from WYSIWYG Instantiation
4.2.4.6. Removing Non-Standard Pragmas
4.2.4.7. Declaring Objects Before Initial Values
4.2.4.8. Confining SystemVerilog Features to SystemVerilog Files
4.2.4.9. Avoiding Assignment Mixing in Always Blocks
4.2.4.10. Avoiding Unconnected, Non-Existent Ports
4.2.4.11. Avoiding Invalid Parameter Ranges
4.2.4.12. Updating Verilog HDL and VHDL Type Mapping
4.2.4.13. Converting Symbolic BDF Files to Acceptable File Formats
5.1. IP Catalog and Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores
5.3. IP General Settings
5.4. Adding IP to IP Catalog
5.5. Best Practices for Intel® FPGA IP
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
5.8. Scripting IP Core Generation
5.9. Modifying an IP Variation
5.10. Upgrading IP Cores
5.11. Simulating Intel® FPGA IP Cores
5.12. Generating Simulation Files for Platform Designer Systems and IP Variants
5.13. Synthesizing IP Cores in Other EDA Tools
5.14. Instantiating IP Cores in HDL
5.15. Support for the IEEE 1735 Encryption Standard
5.16. Related Trainings and Resources
6.1. Viewing Basic Project Information
6.2. Exploring Intel® Quartus® Prime Project Contents
6.3. Managing Project Settings
6.4. Viewing Parameter Settings From the Project Navigator
6.5. Managing Logic Design Files
6.6. Managing Timing Constraints
6.7. Integrating Other EDA Tools
6.8. Exporting Compilation Results
6.9. Archiving Projects
6.10. Command-Line Interface
6.11. Related Trainings
6.8.1. Exporting a Version-Compatible Compilation Database
6.8.2. Importing a Version-Compatible Compilation Database
6.8.3. Creating a Design Partition
6.8.4. Exporting a Design Partition
6.8.5. Reusing a Design Partition
6.8.6. Viewing Quartus Database File Information
6.8.7. Clearing Compilation Results
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6.8.5. Reusing a Design Partition
You can reuse the compilation results of a design partition exported from another Intel® Quartus® Prime project. Reuse of a design partition allows you to share a synthesized or final design block with another designer. Refer to Intel Quartus Prime Pro Edition User Guide: Block-Based Design for more information about reuse of design partitions.
To reuse an exported design partition in another project, you assign the exported partition .qdb to an appropriately configured design partition in the target project via the Design Partition Window:
- Export a design partition with the appropriate snapshot, as Exporting a Design Partition describes.
- Open the target Intel® Quartus® Prime project that you want to reuse the exported partition.
- Click Processing > Start > Start Analysis & Elaboration.
- Click Assignments > Design Partitions Window, and then create a design partition to contain the logic and compilation results of the exported .qdb.
- Click the Partition Database File option for the new partition and select the exported .qdb file.
Figure 69. Partition Database File Setting in Design Partitions Window
- Specify any other properties of the design partition in the Design Partitions Window. The Compiler uses the partition's assigned .qdb as the source.