Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 7/08/2024
Public
Document Table of Contents

6.5.6. HPS External Memory Interface Connections in Arria® 10

You must use the Arria® 10 External Memory Interfaces for HPS Platform Designer (Standard) IP component to connect external SDRAM to the HPS. You can instantiate the Arria® 10 External Memory Interfaces for HPS component in your Platform Designer (Standard) subsystem in addition to the HPS Platform Designer (Standard) component. You must connect the HPS component's EMIF conduit to the Arria® 10 External Memory Interfaces for HPS's EMIF conduit to connect the HPS to external SDRAM memory.

The HPS memory interface is fixed to I/O Banks 2Kand 2J for x40 widths and 2K, 2J, and 2I for x64/x72 widths. When an external SDRAM memory is connected to the HPS, there are restrictions on the availability of unused I/O to the FPGA core in the I/O banks (2K, 2J, 2I) utilized for the HPS memory interface.

When the HPS is connected to external SDRAM memory, no other Arria® 10 External Memory Interface IP instances can be placed in the same I/O column.