Arria® 10 Core Fabric and General Purpose I/Os Handbook

Download PDF
ID 683461
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Logic Array Blocks and Adaptive Logic Modules in Arria® 10 Devices 2. Embedded Memory Blocks in Arria® 10 Devices 3. Variable Precision DSP Blocks in Arria® 10 Devices 4. Clock Networks and PLLs in Arria® 10 Devices 5. I/O and High Speed I/O in Arria® 10 Devices 6. External Memory Interfaces in Arria® 10 Devices 7. Configuration, Design Security, and Remote System Upgrades in Arria® 10 Devices 8. SEU Mitigation for Arria® 10 Devices 9. JTAG Boundary-Scan Testing in Arria® 10 Devices 10. Power Management in Arria® 10 Devices
1. Logic Array Blocks and Adaptive Logic Modules in Arria® 10 Devices x
1.1. LAB 1.2. ALM Operating Modes 1.3. LAB Power Management Techniques 1.4. Logic Array Blocks and Adaptive Logic Modules in Arria® 10 Devices Revision History
1.1. LAB x
1.1.1. MLAB 1.1.2. Local and Direct Link Interconnects 1.1.3. Shared Arithmetic Chain and Carry Chain Interconnects 1.1.4. LAB Control Signals 1.1.5. ALM Resources 1.1.6. ALM Output
1.2. ALM Operating Modes x
1.2.1. Normal Mode 1.2.2. Extended LUT Mode 1.2.3. Arithmetic Mode 1.2.4. Shared Arithmetic Mode
2. Embedded Memory Blocks in Arria® 10 Devices x
2.1. Types of Embedded Memory 2.2. Embedded Memory Design Guidelines for Arria® 10 Devices 2.3. Embedded Memory Features 2.4. Embedded Memory Modes 2.5. Embedded Memory Clocking Modes 2.6. Parity Bit in Embedded Memory Blocks 2.7. Byte Enable in Embedded Memory Blocks 2.8. Memory Blocks Packed Mode Support 2.9. Memory Blocks Address Clock Enable Support 2.10. Memory Blocks Asynchronous Clear 2.11. Memory Blocks Error Correction Code Support 2.12. Embedded Memory Blocks in Arria® 10 Devices Revision History
2.1. Types of Embedded Memory x
2.1.1. Embedded Memory Capacity in Arria® 10 Devices
2.2. Embedded Memory Design Guidelines for Arria® 10 Devices x
2.2.1. Consider the Memory Block Selection 2.2.2. Guideline: Implement External Conflict Resolution 2.2.3. Guideline: Customize Read-During-Write Behavior 2.2.4. Guideline: Consider Power-Up State and Memory Initialization 2.2.5. Guideline: Control Clocking to Reduce Power Consumption
2.2.3. Guideline: Customize Read-During-Write Behavior x
2.2.3.1. Same-Port Read-During-Write Mode 2.2.3.2. Mixed-Port Read-During-Write Mode
2.4. Embedded Memory Modes x
2.4.1. Embedded Memory Configurations for Single-port Mode 2.4.2. Embedded Memory Configurations for Dual-port Modes
2.5. Embedded Memory Clocking Modes x
2.5.1. Clocking Modes for Each Memory Mode 2.5.2. Asynchronous Clears in Clocking Modes 2.5.3. Output Read Data in Simultaneous Read/Write 2.5.4. Independent Clock Enables in Clocking Modes
2.5.1. Clocking Modes for Each Memory Mode x
2.5.1.1. Single Clock Mode 2.5.1.2. Read/Write Clock Mode 2.5.1.3. Input/Output Clock Mode 2.5.1.4. Independent Clock Mode
2.7. Byte Enable in Embedded Memory Blocks x
2.7.1. Byte Enable Controls in Memory Blocks 2.7.2. Data Byte Output 2.7.3. RAM Blocks Operations
2.11. Memory Blocks Error Correction Code Support x
2.11.1. Error Correction Code Truth Table
3. Variable Precision DSP Blocks in Arria® 10 Devices x
3.1. Supported Operational Modes in Arria® 10 Devices 3.2. Resources 3.3. Design Considerations 3.4. Block Architecture 3.5. Operational Mode Descriptions 3.6. Variable Precision DSP Blocks in Arria® 10 Devices Revision History
3.1. Supported Operational Modes in Arria® 10 Devices x
3.1.1. Features
3.3. Design Considerations x
3.3.1. Operational Modes 3.3.2. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic 3.3.3. Accumulator for Fixed-Point Arithmetic 3.3.4. Chainout Adder 3.3.5. DSP Block Cascade Limit in Agilex™ 7 Devices
3.4. Block Architecture x
3.4.1. Input Register Bank 3.4.2. Pipeline Register 3.4.3. Pre-Adder for Fixed-Point Arithmetic 3.4.4. Internal Coefficient for Fixed-Point Arithmetic 3.4.5. Multipliers 3.4.6. Adder 3.4.7. Accumulator and Chainout Adder for Fixed-Point Arithmetic 3.4.8. Systolic Registers for Fixed-Point Arithmetic 3.4.9. Double Accumulation Register for Fixed-Point Arithmetic 3.4.10. Output Register Bank
3.4.1. Input Register Bank x
3.4.1.1. Two Sets of Delay Registers for Fixed-Point Arithmetic
3.5. Operational Mode Descriptions x
3.5.1. Operational Modes for Fixed-Point Arithmetic 3.5.2. Operational Modes for Floating-Point Arithmetic
3.5.1. Operational Modes for Fixed-Point Arithmetic x
3.5.1.1. Independent Multiplier Mode 3.5.1.2. Independent Complex Multiplier 3.5.1.3. Multiplier Adder Sum Mode 3.5.1.4. 18 x 19 Multiplication Summed with 36-Bit Input Mode 3.5.1.5. Systolic FIR Mode
3.5.1.1. Independent Multiplier Mode x
3.5.1.1.1. 18 x 18 or 18 x 19 Independent Multiplier 3.5.1.1.2. 27 x 27 Independent Multiplier
3.5.1.2. Independent Complex Multiplier x
3.5.1.2.1. 18 x 19 Complex Multiplier
3.5.1.5. Systolic FIR Mode x
3.5.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.5.1.5.2. 18-Bit Systolic FIR Mode 3.5.1.5.3. 27-Bit Systolic FIR Mode
3.5.2. Operational Modes for Floating-Point Arithmetic x
3.5.2.1. Single Floating-Point Arithmetic Functions 3.5.2.2. Multiple Floating-Point Arithmetic Functions
3.5.2.1. Single Floating-Point Arithmetic Functions x
3.5.2.1.1. Multiplication Mode 3.5.2.1.2. Adder or Subtract Mode 3.5.2.1.3. Multiply Accumulate Mode
3.5.2.2. Multiple Floating-Point Arithmetic Functions x
3.5.2.2.1. Multiply-Add or Multiply-Subtract Mode 3.5.2.2.2. Vector One Mode 3.5.2.2.3. Vector Two Mode 3.5.2.2.4. Direct Vector Dot Product 3.5.2.2.5. Complex Multiplication
4. Clock Networks and PLLs in Arria® 10 Devices x
4.1. Clock Networks 4.2. Arria® 10 PLLs 4.3. Clock Networks and PLLs in Arria® 10 Devices Revision History
4.1. Clock Networks x
4.1.1. Clock Resources in Arria® 10 Devices 4.1.2. Hierarchical Clock Networks 4.1.3. Types of Clock Networks 4.1.4. Clock Network Sources 4.1.5. Clock Control Block 4.1.6. Clock Power Down 4.1.7. Clock Enable Signals
4.1.3. Types of Clock Networks x
4.1.3.1. Global Clock Networks 4.1.3.2. Regional Clock Networks 4.1.3.3. Periphery Clock Networks
4.1.4. Clock Network Sources x
4.1.4.1. Dedicated Clock Input Pins 4.1.4.2. Internal Logic 4.1.4.3. DPA Outputs 4.1.4.4. HSSI Clock Outputs 4.1.4.5. PLL Clock Outputs
4.1.5. Clock Control Block x
4.1.5.1. Pin Mapping in Arria® 10 Devices 4.1.5.2. GCLK Control Block 4.1.5.3. RCLK Control Block 4.1.5.4. PCLK Control Block
4.2. Arria® 10 PLLs x
4.2.1. PLL Usage 4.2.2. PLL Architecture 4.2.3. PLL Control Signals 4.2.4. Clock Feedback Modes 4.2.5. Clock Multiplication and Division 4.2.6. Programmable Phase Shift 4.2.7. Programmable Duty Cycle 4.2.8. PLL Cascading 4.2.9. Reference Clock Sources 4.2.10. Clock Switchover 4.2.11. PLL Reconfiguration and Dynamic Phase Shift
4.2.3. PLL Control Signals x
4.2.3.1. Reset 4.2.3.2. Locked
4.2.10. Clock Switchover x
4.2.10.1. Automatic Switchover 4.2.10.2. Automatic Switchover with Manual Override 4.2.10.3. Manual Clock Switchover 4.2.10.4. Guidelines
5. I/O and High Speed I/O in Arria® 10 Devices x
5.1. I/O and Differential I/O Buffers in Arria® 10 Devices 5.2. I/O Standards and Voltage Levels in Arria® 10 Devices 5.3. Altera FPGA I/O IP Cores for Arria® 10 Devices 5.4. I/O Resources in Arria® 10 Devices 5.5. Architecture and General Features of I/Os in Arria® 10 Devices 5.6. High Speed Source-Synchronous SERDES and DPA in Arria® 10 Devices 5.7. Using the I/Os and High Speed I/Os in Arria® 10 Devices 5.8. I/O and High Speed I/O in Arria® 10 Devices Revision History
5.2. I/O Standards and Voltage Levels in Arria® 10 Devices x
5.2.1. I/O Standards Support for FPGA I/O in Arria® 10 Devices 5.2.2. I/O Standards Support for HPS I/O in Arria® 10 Devices 5.2.3. I/O Standards Voltage Levels in Arria® 10 Devices
5.4. I/O Resources in Arria® 10 Devices x
5.4.1. GPIO Banks, SERDES, and DPA Locations in Arria® 10 Devices 5.4.2. GPIO Buffers and LVDS Channels in Arria® 10 Devices 5.4.3. I/O Banks Groups in Arria® 10 Devices 5.4.4. I/O Vertical Migration for Arria® 10 Devices
5.4.2. GPIO Buffers and LVDS Channels in Arria® 10 Devices x
5.4.2.1. FPGA I/O Resources in Arria® 10 GX Packages 5.4.2.2. FPGA I/O Resources in Arria® 10 GT Packages 5.4.2.3. FPGA I/O Resources in Arria® 10 SX Packages
5.4.3. I/O Banks Groups in Arria® 10 Devices x
5.4.3.1. I/O Banks for Arria® 10  GX Devices 5.4.3.2. I/O Banks for Arria® 10  GT Devices 5.4.3.3. I/O Banks for Arria® 10  SX Devices
5.4.4. I/O Vertical Migration for Arria® 10 Devices x
5.4.4.1. Verifying Pin Migration Compatibility
5.5. Architecture and General Features of I/Os in Arria® 10 Devices x
5.5.1. I/O Element Structure in Arria® 10 Devices 5.5.2. Features of I/O Pins in Arria® 10 Devices 5.5.3. Programmable IOE Features in Arria® 10 Devices 5.5.4. On-Chip I/O Termination in Arria® 10 Devices 5.5.5. External I/O Termination for Arria® 10 Devices
5.5.1. I/O Element Structure in Arria® 10 Devices x
5.5.1.1. I/O Bank Architecture in Arria® 10 Devices 5.5.1.2. I/O Buffer and Registers in Arria® 10 Devices
5.5.2. Features of I/O Pins in Arria® 10 Devices x
5.5.2.1. Open-Drain Output 5.5.2.2. Bus-Hold Circuitry 5.5.2.3. Weak Pull-up Resistor
5.5.3. Programmable IOE Features in Arria® 10 Devices x
5.5.3.1. Programmable Current Strength 5.5.3.2. Programmable Output Slew Rate Control 5.5.3.3. Programmable IOE Delay 5.5.3.4. Programmable Open-Drain Output 5.5.3.5. Programmable Pre-Emphasis 5.5.3.6. Programmable Differential Output Voltage
5.5.4. On-Chip I/O Termination in Arria® 10 Devices x
5.5.4.1. RS OCT without Calibration in Arria® 10 Devices 5.5.4.2. RS OCT with Calibration in Arria® 10 Devices 5.5.4.3. RT OCT with Calibration in Arria® 10 Devices 5.5.4.4. Dynamic OCT 5.5.4.5. Differential Input RD OCT 5.5.4.6. OCT Calibration Block in Arria® 10 Devices
5.5.5. External I/O Termination for Arria® 10 Devices x
5.5.5.1. Single-Ended I/O Termination 5.5.5.2. Differential I/O Termination for Arria® 10 Devices
5.5.5.2. Differential I/O Termination for Arria® 10 Devices x
5.5.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 5.5.5.2.2. LVDS, RSDS, and Mini-LVDS Termination 5.5.5.2.3. LVPECL Termination
5.6. High Speed Source-Synchronous SERDES and DPA in Arria® 10 Devices x
5.6.1. Arria® 10 LVDS SERDES Usage Modes 5.6.2. SERDES Circuitry 5.6.3. SERDES I/O Standards Support in Arria® 10 Devices 5.6.4. Differential Transmitter in Arria® 10 Devices 5.6.5. Differential Receiver in Arria® 10 Devices 5.6.6. PLLs and Clocking for Arria® 10 Devices 5.6.7. Timing and Optimization for Arria® 10 Devices
5.6.4. Differential Transmitter in Arria® 10 Devices x
5.6.4.1. Transmitter Blocks in Arria® 10 Devices 5.6.4.2. Serializer Bypass for DDR and SDR Operations
5.6.5. Differential Receiver in Arria® 10 Devices x
5.6.5.1. Receiver Blocks in Arria® 10 Devices 5.6.5.2. Receiver Modes in Arria® 10 Devices
5.6.5.1. Receiver Blocks in Arria® 10 Devices x
5.6.5.1.1. DPA Block 5.6.5.1.2. Synchronizer 5.6.5.1.3. Data Realignment Block (Bit Slip) 5.6.5.1.4. Deserializer
5.6.5.2. Receiver Modes in Arria® 10 Devices x
5.6.5.2.1. Non-DPA Mode 5.6.5.2.2. DPA Mode 5.6.5.2.3. Soft-CDR Mode
5.6.6. PLLs and Clocking for Arria® 10 Devices x
5.6.6.1. Clocking Differential Transmitters 5.6.6.2. Clocking Differential Receivers 5.6.6.3. Guideline: LVDS Reference Clock Source 5.6.6.4. Guideline: Use PLLs in Integer PLL Mode for LVDS 5.6.6.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only 5.6.6.6. Guideline: Pin Placement for Differential Channels 5.6.6.7. LVDS Interface with External PLL Mode
5.6.6.2. Clocking Differential Receivers x
5.6.6.2.1. Guideline: Clocking DPA Interfaces Spanning Multiple I/O Banks 5.6.6.2.2. Guideline: I/O PLL Reference Clock Source for DPA or Non-DPA Receiver
5.6.6.7. LVDS Interface with External PLL Mode x
5.6.6.7.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.6.6.7.2. IOPLL Parameter Values for External PLL Mode 5.6.6.7.3. Connection between IOPLL and LVDS SERDES in External PLL Mode
5.6.7. Timing and Optimization for Arria® 10 Devices x
5.6.7.1. Source-Synchronous Timing Budget
5.6.7.1. Source-Synchronous Timing Budget x
5.6.7.1.1. Differential Data Orientation 5.6.7.1.2. Differential I/O Bit Position 5.6.7.1.3. Transmitter Channel-to-Channel Skew 5.6.7.1.4. Receiver Skew Margin for Non-DPA Mode
5.7. Using the I/Os and High Speed I/Os in Arria® 10 Devices x
5.7.1. I/O and High-Speed I/O General Guidelines for Arria® 10 Devices 5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards 5.7.3. Guideline: Maximum Current Driving I/O Pins While Turned Off and During Power Sequencing 5.7.4. Guideline: Using the I/O Pins in HPS Shared I/O Banks 5.7.5. Guideline: Maximum DC Current Restrictions 5.7.6. Guideline: LVDS SERDES IP Core Instantiation 5.7.7. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode 5.7.8. Guideline: Minimizing High Jitter Impact on Arria® 10 GPIO Performance 5.7.9. Guideline: Usage of I/O Bank 2A for External Memory Interfaces
5.7.1. I/O and High-Speed I/O General Guidelines for Arria® 10 Devices x
5.7.1.1. Guideline: VREF Sources and VREF Pins 5.7.1.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 5.7.1.3. Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin
5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards x
5.7.2.1. Non-Voltage-Referenced I/O Standards 5.7.2.2. Voltage-Referenced I/O Standards 5.7.2.3. Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
6. External Memory Interfaces in Arria® 10 Devices x
6.1. Key Features of the Arria® 10 External Memory Interface Solution 6.2. Memory Standards Supported by Arria® 10 Devices 6.3. External Memory Interface Widths in Arria® 10 Devices 6.4. External Memory Interface I/O Pins in Arria® 10 Devices 6.5. Memory Interfaces Support in Arria® 10 Device Packages 6.6. External Memory Interface IP Support in Arria® 10 Devices 6.7. External Memory Interface Architecture of Arria® 10 Devices 6.8. External Memory Interface in Arria® 10 Devices Revision History
6.4. External Memory Interface I/O Pins in Arria® 10 Devices x
6.4.1. Guideline: Usage of I/O Bank 2A for External Memory Interfaces
6.5. Memory Interfaces Support in Arria® 10 Device Packages x
6.5.1. Arria® 10 Package Support for DDR3 x40 with ECC 6.5.2. Arria® 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank 6.5.3. Arria® 10 Package Support for DDR4 x40 with ECC 6.5.4. Arria® 10 Package Support for DDR4 x72 with ECC Single-Rank 6.5.5. Arria® 10 Package Support for DDR4 x72 with ECC Dual-Rank 6.5.6. HPS External Memory Interface Connections in Arria® 10
6.5.6. HPS External Memory Interface Connections in Arria® 10 x
6.5.6.1. Arria® 10 Package Support for DDR3 x40 with ECC for HPS 6.5.6.2. Arria® 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank for HPS 6.5.6.3. Arria® 10 Package Support for DDR4 x40 with ECC for HPS 6.5.6.4. Arria® 10 Package Support for DDR4 x72 with ECC Single-Rank for HPS
6.6. External Memory Interface IP Support in Arria® 10 Devices x
6.6.1. Ping Pong PHY IP
6.7. External Memory Interface Architecture of Arria® 10 Devices x
6.7.1. I/O Bank 6.7.2. I/O AUX
6.7.1. I/O Bank x
6.7.1.1. Hard Memory Controller 6.7.1.2. Delay-Locked Loop 6.7.1.3. Sequencer 6.7.1.4. Clock Tree 6.7.1.5. I/O Lane
6.7.1.1. Hard Memory Controller x
6.7.1.1.1. Hard Memory Controller Features 6.7.1.1.2. Main Control Path 6.7.1.1.3. Data Buffer Controller
6.7.1.5. I/O Lane x
6.7.1.5.1. DQS Logic Block
7. Configuration, Design Security, and Remote System Upgrades in Arria® 10 Devices x
7.1. Enhanced Configuration and Configuration via Protocol 7.2. Configuration Schemes 7.3. Configuration Details 7.4. Remote System Upgrades Using Active Serial Scheme 7.5. Design Security 7.6. Configuration, Design Security, and Remote System Upgrades in Arria® 10 Devices Revision History
7.2. Configuration Schemes x
7.2.1. Active Serial Configuration 7.2.2. Passive Serial Configuration 7.2.3. Fast Passive Parallel Configuration 7.2.4. JTAG Configuration
7.2.1. Active Serial Configuration x
7.2.1.1. DATA Clock (DCLK) 7.2.1.2. Active Serial Single-Device Configuration 7.2.1.3. Active Serial Multi-Device Configuration 7.2.1.4. Active Serial Configuration with Multiple EPCQ-L Devices 7.2.1.5. Using EPCQ-L Devices
7.2.1.3. Active Serial Multi-Device Configuration x
7.2.1.3.1. Pin Connections and Guidelines 7.2.1.3.2. Using Multiple Configuration Data
7.2.1.5. Using EPCQ-L Devices x
7.2.1.5.1. Controlling EPCQ-L Devices 7.2.1.5.2. Trace Length Guideline 7.2.1.5.3. Programming EPCQ-L Devices
7.2.2. Passive Serial Configuration x
7.2.2.1. Passive Serial Single-Device Configuration Using an External Host 7.2.2.2. Passive Serial Single-Device Configuration Using an Intel FPGA Download Cable 7.2.2.3. Passive Serial Multi-Device Configuration
7.2.2.3. Passive Serial Multi-Device Configuration x
7.2.2.3.1. Pin Connections and Guidelines 7.2.2.3.2. Using Multiple Configuration Data 7.2.2.3.3. Using One Configuration Data 7.2.2.3.4. Using PC Host and Download Cable
7.2.3. Fast Passive Parallel Configuration x
7.2.3.1. Fast Passive Parallel Single-Device Configuration 7.2.3.2. Fast Passive Parallel Multi-Device Configuration
7.2.3.2. Fast Passive Parallel Multi-Device Configuration x
7.2.3.2.1. Pin Connections and Guidelines 7.2.3.2.2. Using Multiple Configuration Data 7.2.3.2.3. Using One Configuration Data
7.2.4. JTAG Configuration x
7.2.4.1. JTAG Single-Device Configuration 7.2.4.2. JTAG Multi-Device Configuration
7.2.4.2. JTAG Multi-Device Configuration x
7.2.4.2.1. Pin Connections and Guidelines 7.2.4.2.2. Using a Download Cable
7.3. Configuration Details x
7.3.1. MSEL Pin Settings 7.3.2. CLKUSR 7.3.3. Configuration Sequence 7.3.4. Configuration Timing Waveforms 7.3.5. Estimating Configuration Time 7.3.6. Device Configuration Pins 7.3.7. Configuration Data Compression
7.3.3. Configuration Sequence x
7.3.3.1. Power Up 7.3.3.2. Reset 7.3.3.3. Configuration 7.3.3.4. Configuration Error Handling 7.3.3.5. Initialization 7.3.3.6. User Mode
7.3.3.3. Configuration x
7.3.3.3.1. Configuration Error Detection
7.3.4. Configuration Timing Waveforms x
7.3.4.1. FPP Configuration Timing 7.3.4.2. AS Configuration Timing 7.3.4.3. PS Configuration Timing
7.3.6. Device Configuration Pins x
7.3.6.1. I/O Standards and Drive Strength for Configuration Pins 7.3.6.2. Configuration Pin Options in the Quartus® Prime Software
7.3.7. Configuration Data Compression x
7.3.7.1. Enabling Compression Before Design Compilation 7.3.7.2. Enabling Compression After Design Compilation 7.3.7.3. Using Compression in Multi-Device Configuration
7.4. Remote System Upgrades Using Active Serial Scheme x
7.4.1. Configuration Images 7.4.2. Configuration Sequence in the Remote Update Mode 7.4.3. Remote System Upgrade Circuitry 7.4.4. Enabling Remote System Upgrade Circuitry 7.4.5. Remote System Upgrade Registers 7.4.6. Remote System Upgrade State Machine 7.4.7. User Watchdog Timer
7.4.5. Remote System Upgrade Registers x
7.4.5.1. Control Register 7.4.5.2. Status Register
7.5. Design Security x
7.5.1. Security Key Types 7.5.2. Security Modes 7.5.3. Arria® 10 Qcrypt Security Tool 7.5.4. Design Security Implementation Steps
7.5.2. Security Modes x
7.5.2.1. JTAG Secure Mode
8. SEU Mitigation for Arria® 10 Devices x
8.1. Arria® 10 SEU Mitigation Overview 8.2. Arria® 10 SEU Mitigation Techniques 8.3. CRAM Error Detection Settings Reference 8.4. Specifications 8.5. SEU Mitigation for Arria® 10 Devices Revision History
8.1. Arria® 10 SEU Mitigation Overview x
8.1.1. Mitigating Single Event Upset
8.1.1. Mitigating Single Event Upset x
8.1.1.1. Configuration RAM 8.1.1.2. Embedded Memory 8.1.1.3. Failure Rates
8.2. Arria® 10 SEU Mitigation Techniques x
8.2.1. Mitigating SEU Effects in Configuration RAM 8.2.2. Mitigating SEU Effects in Embedded User RAM 8.2.3. Triple-Module Redundancy 8.2.4. Quartus® Prime Software SEU FIT Reports
8.2.1. Mitigating SEU Effects in Configuration RAM x
8.2.1.1. Error Detection Cyclic Redundancy Check 8.2.1.2. SEU Sensitivity Processing 8.2.1.3. Hierarchy Tagging 8.2.1.4. Evaluating Your System’s Response to Functional Upsets 8.2.1.5. Recovering from CRC Errors
8.2.1.1. Error Detection Cyclic Redundancy Check x
8.2.1.1.1. Column-Based and Frame-Based Check-Bits 8.2.1.1.2. Error Message Register 8.2.1.1.3. CRC_ERROR Pin Behavior
8.2.1.5. Recovering from CRC Errors x
8.2.1.5.1. Enabling Error Correction (Internal Scrubbing)
8.2.2. Mitigating SEU Effects in Embedded User RAM x
8.2.2.1. Configuring RAM to Enable ECC
8.2.4. Quartus® Prime Software SEU FIT Reports x
8.2.4.1. SEU FIT Parameters Report 8.2.4.2. Projected SEU FIT by Component Usage Report 8.2.4.3. Enabling the Projected SEU FIT by Component Usage Report
8.2.4.2. Projected SEU FIT by Component Usage Report x
8.2.4.2.1. Component FIT Rates 8.2.4.2.2. Raw FIT 8.2.4.2.3. Utilized FIT 8.2.4.2.4. Mitigated FIT 8.2.4.2.5. Architectural Vulnerability Factor
8.4. Specifications x
8.4.1. Error Detection Frequency 8.4.2. Error Detection Time 8.4.3. EMR Update Interval 8.4.4. Error Correction Time
9. JTAG Boundary-Scan Testing in Arria® 10 Devices x
9.1. BST Operation Control 9.2. I/O Voltage for JTAG Operation 9.3. Performing BST 9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry 9.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing 9.6. IEEE Std. 1149.1 Boundary-Scan Register 9.7. JTAG Boundary-Scan Testing in Arria® 10 Devices Revision History
9.1. BST Operation Control x
9.1.1. IDCODE 9.1.2. Supported JTAG Instruction 9.1.3. JTAG Secure Mode 9.1.4. JTAG Private Instruction
9.6. IEEE Std. 1149.1 Boundary-Scan Register x
9.6.1. Boundary-Scan Cells of an Arria® 10 Device I/O Pin 9.6.2. IEEE Std. 1149.6 Boundary-Scan Register
10. Power Management in Arria® 10 Devices x
10.1. Power Consumption 10.2. Power Reduction Techniques 10.3. Power Sense Line 10.4. Voltage Sensor 10.5. Temperature Sensing Diode 10.6. Power-On Reset Circuitry 10.7. Power Sequencing Considerations for Arria® 10 Devices 10.8. Power Supply Design 10.9. Power Management in Arria® 10 Devices Revision History
10.1. Power Consumption x
10.1.1. Dynamic Power Equation
10.2. Power Reduction Techniques x
10.2.1. SmartVID 10.2.2. Programmable Power Technology 10.2.3. Low Static Power Device Grades 10.2.4. SmartVID Feature Implementation
10.4. Voltage Sensor x
10.4.1. Input Signal Range for External Analog Signal 10.4.2. Using Voltage Sensor in Arria® 10 Devices
10.4.1. Input Signal Range for External Analog Signal x
10.4.1.1. Unipolar Input Mode
10.4.2. Using Voltage Sensor in Arria® 10 Devices x
10.4.2.1. Accessing the Voltage Sensor Using FPGA Core Access 10.4.2.2. Voltage Sensor Transfer Function
10.4.2.1. Accessing the Voltage Sensor Using FPGA Core Access x
10.4.2.1.1. Configuration Registers for the Core Access Mode 10.4.2.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11 10.4.2.1.3. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
10.5. Temperature Sensing Diode x
10.5.1. Internal Temperature Sensing Diode 10.5.2. External Temperature Sensing Diode 10.5.3. Design Consideration
10.5.1. Internal Temperature Sensing Diode x
10.5.1.1. Transfer Function for Internal TSD
10.5.3. Design Consideration x
10.5.3.1. Comparing Temperature Readouts of Arria® 10 External TSD and Arria® 10 Internal Temperature Sensor
10.6. Power-On Reset Circuitry x
10.6.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
10.7. Power Sequencing Considerations for Arria® 10 Devices x
10.7.1. Power-Up Sequence Requirements for Arria® 10 Devices 10.7.2. Power-Down Sequence Recommendations and Requirements for Arria® 10 Devices
1. Logic Array Blocks and Adaptive Logic Modules in Arria® 10 Devices
2. Embedded Memory Blocks in Arria® 10 Devices
3. Variable Precision DSP Blocks in Arria® 10 Devices
4. Clock Networks and PLLs in Arria® 10 Devices
5. I/O and High Speed I/O in Arria® 10 Devices
6. External Memory Interfaces in Arria® 10 Devices
7. Configuration, Design Security, and Remote System Upgrades in Arria® 10 Devices
8. SEU Mitigation for Arria® 10 Devices
9. JTAG Boundary-Scan Testing in Arria® 10 Devices
10. Power Management in Arria® 10 Devices

7.6. Configuration, Design Security, and Remote System Upgrades in Arria® 10 Devices Revision History

Document Version Changes
2024.07.08
  • Updated the description for the following timing diagrams.
    • FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
    • FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
    • PS Configuration Timing Waveform
  • Updated the AS Configuration Timing Waveform timing diagram.
2020.09.25 Updated Table: Available Configuration Clock Source and Transceiver Calibration CLKUSR Frequency for Arria® 10 Devices to update the supported clock sources and transceiver calibration CLKUSR frequency for AS.
2020.06.30 Updated the Active Serial Multi-Device Configuration section on determining the DCLK frequency for slave devices.
2020.03.31 Updated the User Mode topic.
2019.12.30 Added note to clarify users should use 12 mA drive strength IBIS model when simulating the AS_DATA[0]/ASDO, AS_DATA[3:1], and DCLK configuration pins for 1.8V LVCMOS I/O standard in the I/O Standards and Drive Strength for Configuration Pins table.
2019.03.28 Updated the note in the Trace Length Guideline topic.
2019.01.23

Added a link to the Intel® Supported Configuration Devices section of the Device Configuration - Support Center page on the Intel® website.

2019.01.11
  • Added a note in CLKUSR to state that CLKUSR cannot be used as the reference clock for PLL.
  • Updated Table: Configuration Pin Summary for Arria® 10 Devices to update the note for nIO_PULLUP.
2018.08.28
  • Added Multiple Configuration Devices Support section.
  • Updated the description in the Using Multiple Configuration Data section for active serial multi-device configuration.
  • Updated the description in the Using Multiple Configuration Data section for fast passive parallel multi-device configuration.
  • Updated Table: I/O Standards and Drive Strength for Configuration Pins.
2018.03.09 Updated Configuration Pin Summary for Arria® 10 Devices table to indicate CLKUSR and nCEO pins are optional.
Date Version Changes
December 2017 2017.12.15
  • Removed LOCK and UNLOCK instructions from Mandatory IEEE Standard 1149.1 BST JTAG Instructions.
  • Updated Single Device FPP Configuration Using an External Host, Multiple Device FPP Configuration Using an External Host When Both Devices Receive a Different Set of Configuration Data, and Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same Data figures.
March 2017 2017.03.15
  • Rebranded as Intel.
  • Added note to nIO_PULLUP pin in Configuration Pin Summary for Arria® 10 Devices table.
  • Added pull-up resistor between nCEO and nCE in Multiple Device FPP Configuration Using an External Host When Both Devices Receive a Different Set of Configuration Data figure.
  • Added pull-up resistor between nCEO and nCE in Multiple Device AS Configuration When Both Devices in the Chain Receive Different Sets of Configuration Data figure.
  • Added pull-up resistor between nCEO and nCE in Multiple Device PS Configuration when Both Devices Receive Different Sets of Configuration Data figure.
October 2016 2016.10.31
  • Updated the drive strength for configuration pins:
    • DCLK—from 1.8 V CMOS 12 mA to 1.8 V CMOS 24 mA.
    • NCSO[2..0]—from 1.8 V CMOS 8 mA to 1.8 V CMOS 12 mA.
    • AS_DATA0/ASD0, AS_DATA1, AS_DATA2, and AS_DATA3—from 1.8 V CMOS 8 mA to 1.8 V CMOS 24 mA.
June 2016 2016.05.13
  • Updated design security features and approaches.
  • Updated instances of EX_JTAG_SECURE to EXT_JTAG_SECURE
  • Added list of mandatory and non-mandatory IEEE Standard 1149.1 JTAG BST instructions.
  • Updated security modes available in Arria 10 devices and instructions to enable them.
  • Added the Qrypt security tool information.
May 2016 2016.05.02
  • Added FPP and PS configuration time estimation to Estimating Configuration Time and moved subsection under Configuration Details section.
  • Added note on possible PCIe timing violation when using direct-to-application.
  • Added note on recommending user to set a fixed configuration image start address.
  • Added I/O Standards and Drive Strength for Configuration Pins section.
  • Updated AS configuration timing waveform to include nCSO.
  • Updated TSU and TDH in AS configuration timing waveform.
December 2015 2015.12.14
  • Updated CLKUSR information.
  • Moved CLKUSR subsection from Active Serial Configuration to Configuration Details.
November 2015 2015.11.02
  • Updated the term configuration mode to configuration scheme for consistency.
  • Added link at MSEL pin setting to Arria 10 Hard Processor System Technical Reference Manual.
  • Combined PS and FPP row in MSEL pin settings table. Both schemes have the same MSEL pin setting.
  • Added description to MSEL pin setting table for configuration via HPS to use PS or FPP MSEL pin setting.
  • Updated configuration modes and features table to include Yes for partial reconfiguration in JTAG, AS and PS configuration mode together with a footnote mentioning only if partial reconfiguration is configured as internal host.
  • Updated note about compression and encryption cannot be used a the same time for all configuration scheme.
  • Updated timing waveforms FPP, AS and PS to include pre power-up state.
  • Removed step to select Remote from the Configuration mode list in the Configuration page of the Device and Pin Options dialog box in the Quartus II software.
  • Added note about setting the MSEL pin to active serial to prevent EPCQ-L ID read failure during SFL programming.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04
  • Added Timing waveforms for FPP, AS and PS configuration.
  • Updated 'Trace Length and Loading' to 'Trace Length Guideline' and remove loading contents.
  • Added link to Arria 10 Device Datasheet for loading information.
  • Update FPP to support 8 and 32 bits in 'Configuration Modes and Features of Arria 10 Devices'.
  • Added note in 'Design Security' and 'Configuration Data Compression' about compression and encryption cannot be used a the same time.
January 2015 2015.01.23
  • Updated CLKUSR pin usage during AS configuration at 100 MHz.
  • Updated Max clock rate of PS, FPP x8, FPP x16 and Configuration via HPS from 125 MHz to 100 MHz.
  • Updated Remote System Upgrade Circuitry diagram by replacing RU_SHIFTnLD and RU_CAPTnUPDT to RU_CTL[1:0].
  • Updated ALTREMOTE_UPDATE megafunction to Altera remote Update IP Core.
  • Updated user watchdog time-out value from 34..46 to 34..45.
  • Updated nIO_PULLUP to be powered by VCC.
  • Added note to Max Data Rate in Configuration Modes and Features of Arria® 10 Devices table.
August 2014 2014.08.18
  • Added the Active Serial Configuration with Multiple EPCQ-L Devices section.
  • Removed the Unique Chip ID section.
  • Updated the JTAG Configuration section to include details on the USB-Blaster download cable support.
  • Updated the Power Up section.
  • Updated Configuration Images section to include start address.
  • Updated the Configuration Sequence in the Remote Update Mode section.
  • Updated the Remote System Upgrade State Machine section.
  • Updated Figure 7-18: JTAG Configuration of a Single Device Using a Microprocessor to update the power reference of the JTAG pins.
  • Updated Figure 7-20: Configuration Sequence for Arria 10 Devices.
  • Updated Figure 7-22: Arria 10 Remote System Upgrade Block Diagram.
  • Updated Table 7-1: Configuration Modes and Features of Arria 10 Devices to update the supported clock rate for Partial Reconfiguration.
  • Updated Table 7-3: MSEL Pin Settings for Each Configuration Scheme of Arria 10 Devices to include the supported VCCPGM voltages for the FPP and PS configuration schemes.
  • Updated Table 7-6: Remote System Upgrade Registers to update the description for the shift, control, update, and status registers.
  • Updated Table 7-7: Control Register Bits.
  • Removed the Unique Chip ID section.
December 2013 2013.12.02 Initial release.
Level Two Title