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1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Intel® FPGA IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.7. JESD204B Design Examples
3.8. JESD204B IP Design Considerations
3.9. JESD204B Intel® FPGA IP Parameters
3.10. JESD204B IP Component Files
3.11. JESD204B IP Testbench
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3.8.2. Pin Assignments
Set the pin assignments before you compile to provide direction to the Quartus® Prime software Fitter tool. You must also specify the signals that should be assigned to device I/O pins.
You can create virtual pins to avoid making specific pin assignments for top-level signals. This is useful when you want to perform compilation, but are not ready to map the design to hardware. Intel® recommends that you create virtual pins for all unused top-level signals to improve timing closure.
Note: Do not create virtual pins for the clock or reset signals.
For Agilex™ 7 and Stratix® 10 E-tile devices, use the E-Tile Channel Placement Tool to get a valid pinout. Specify the transceiver mode as PMA direct - NRZ.
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