In this section, the PDN post-layout simulation is shown in the Methodology for Device PDN and Transient Noise Analysis figure for any Agilex™ 7 device family board design and system-level PDN simulation.

Altera recommends you to follow the above-mentioned guidelines to design all power rails on the PCB with the recommended decoupling capacitors, voltage regulators, and LC filtering. In the post-layout phase, Altera recommends you to do the IR drop and transient (time domain) PDN analysis for PCB only. This means, unconventionally, Altera do not recommend impedance target and frequency target analysis (frequency domain simulation) for the Agilex™ 7 device.

To ensure the PDN design performance is within the required tolerance or specification in the Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance , Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance , and Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance tables, time domain post-layout PDN simulation for some critical power nets such as VCC core, VCCP, VCCPT, VCCIO_PIO, VCCH, and power rails for E-Tile, P-Tile, F-Tile, and R-Tile must be performed.

PDN time domain simulation is only performed on PCB from voltage regulator to package ball. Therefore, package, OPDs, and on-chip models are not required for the PDN time domain simulation.

The following steps show the time domain PDN simulation (as shown in the Time Domain PDN Test Bench Example for Agilex™ 7 AGF014 VCC Core figure):

1. Obtain the implemented VRM SPICE model for the target power rail.
2. Extract post-layout PCB model (HSPICE or scattering parameters by using tools such as PowerSI) of the PCB with decoupling capacitors and LC filtering from the voltage regulator (including VRM recommended bulk decoupling capacitors by vendor) to package pin (if use of scattering parameters, the PCB model shall be extracted from DC up to 1 GHz). Altera recommends you to convert scattering parameters to circuit model by use of any broadband Spice or IDEM tool to avoid problematic simulation. To avoid simulation divergence, you shall include the small to medium decoupling capacitors on PCB extraction and define ports for the large and bulk capacitors on the PCB when extracting its model. Then, you add the large/bulk capacitors (in the format of spice models) externally in the schematic (as explained in step 3).
3. Build a schematic in any possible EDA tool (Keysight ADS or Cadence or LTspice or Simplix) with the voltage regulator model (possible HSPICE model) and PCB model extracted from previous step.
   • This schematic represents the voltage regulator plus the PCB or decoupling capacitors model up to package pins.
   • Package, OPDs, or die model are not built into this schematic (Step load at package pin covers frequencies for only PCB, which means high frequency current components are eliminated through package and on-die).
   • Connect the sense pins from the package pin feedback to the voltage regulator sense pins.
4. Connect the maximum step load current at the package pins shown in the Agilex™ 7 Device Family Transient and Step Load Specifications at Package Pin table (for example, for Agilex™ 7 AGF014 core, 200A/µs slew rate and step load of 17A).
5. Probe voltage drop at the package pin to see if the power rail specification in the Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance , Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance , and Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance tables is met (for example, for VCC core, the DC+AC voltage tolerance is ±3%).
   • If not meeting the package power rail tolerance or specification in the Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance , Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance , and Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance tables, you must check the PCB and adjust the decoupling capacitors or locations.

You must notice that the Time Domain PDN Test Bench Example for Agilex™ 7 AGF014 VCC Core figure shows a simplified schematic for the PDN transient simulation. In order to avoid non-convergence condition in TD simulation, Altera recommends you to only include small decoupling capacitors in the PCB model extraction and define ports for large/bulk decoupling capacitors at PCB level and add them to the schematic in the Time Domain PDN Test Bench Example for Agilex™ 7 AGF014 VCC Core figure manually.

The recommended step load along with the static current (obtained from PTC) in a format of a pulse for each power rail is added to power rail ports in the PDN simulation schematic (e.g., Time Domain PDN Test Bench Example for Agilex™ 7 AGF014 VCC Core figure) and the voltage droop and overshoot are measured against the specification listed in Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance , Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance , and Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance tables.

The PDN IR drop analysis is a DC simulation and must be performed on all power rails on the PCB up to package pins to meet the electrical specifications listed in the respective Agilex™ 7 FPGAs and SoCs Device Data Sheets.

The Reference Stackup figure shows the reference stackup used in the PDN design guideline and FPGA decoupling capacitors extraction. However, the FPGA PDN performance is also validated with a thicker PCB such the DK-SI-AGF014E3ES board designed in-house.