Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

3.1. Board Decoupling Capacitors and Power Flooding Guides

In addition to on-package decoupling (OPD) (as land-side capacitor (LSC) and die-side capacitor (DSC)), the Agilex™ 7 device family also offers a cavity site or state to place large size back side capacitors as close as possible to the die or package to improve transient voltage droop response and reduce second or third voltage droop. A total of 15 decoupling capacitors (refer to the Agilex™ 7 FPGA F-Series, I-Series, and M-Series Decoupling Capacitors Summary table, the bottom side capacitors for VCC core and VCCH) can be added into the Agilex™ 7 AGF014 Development Kit Board cavity including 9x 0805 47uF (for VCC core) and 6x 0603 22uF (for VCCH) as shown in the Back-side Board Cavity with Large Size Decoupling Capacitors for PCB without Socket, Thin Stackup, and the Use of Micro Via ( Agilex™ 7 AGF014 PCIe* Development Kit) figure.

The Back-side Board Cavity with Large Size Decoupling Capacitors for PCB without Socket, Thin Stackup, and the Use of Micro Via ( Agilex™ 7 AGF014 PCIe* Development Kit) figure is an example of a decoupling capacitor placement scheme or connection within cavity on the bottom-layer for a PCB designed for the Agilex™ 7 AGF014 PCIe* Development Kit without socket and the use of micro via. The top layer in the Back-side Board Cavity with Large Size Decoupling Capacitors for PCB without Socket, Thin Stackup, and the Use of Micro Via ( Agilex™ 7 AGF014 PCIe* Development Kit) figure is assigned for VCC core power and the GND pins on top layer within the decoupling capacitor mounting are connected to the second layer (ground) through a micro via.

Figure 4.  Back-side Board Cavity with Large Size Decoupling Capacitors for PCB without Socket, Thin Stackup, and the Use of Micro Via ( Agilex™ 7 AGF014 PCIe* Development Kit)

Because of the location of the cavity capacitors on the bottom side, several GND balls cannot have vias in pad, for stackup without the use of micro via. To ensure that we do not reduce the package current capability, and that we have a low-return inductance path, add a ground island on the top layer connecting those floating balls to adjacent GND vias, as illustrated in the Back-side Board Cavity with Large Size Decoupling Capacitors, Thick Stackup, and the Use of Through Via ( Agilex™ 7 AGF014 Signal Integrity Development Kit) figure.

The Back-side Board Cavity with Large Size Decoupling Capacitors, Thick Stackup, and the Use of Through Via ( Agilex™ 7 AGF014 Signal Integrity Development Kit) figure is an example of decoupling capacitors scheme or connection within the cavity on the bottom layer for a PCB designed of Agilex™ 7 AGF014 Signal Integrity Development Kit without socket and the use of only through via for GND pins.

Figure 5.  Back-side Board Cavity with Large Size Decoupling Capacitors, Thick Stackup, and the Use of Through Via ( Agilex™ 7 AGF014 Signal Integrity Development Kit)

If some of the required decoupling capacitors within the cavity cannot be placed due to some restriction, you can make specification within the pin field to place them as long as they are close to the cavity area.

In addition, other recommended 0201 and 0402 decoupling capacitors can be placed in the via field (FPGA pin field) on bottom layer inside the package shadow. The board side decoupling capacitors (FPGA periphery) recommendation for all rails can be placed either on top layer or bottom layer close to the edge of FPGA device.

This is a summary of the recommended decoupling capacitors placement within cavity for the Agilex™ 7 AGF012 and AGF014 device family:

  • VCC core cavity decoupling capacitors on bottom side:
    • Thick PCB: 9x 0805 47µF
    • Thin PCB: 5x 0805 47µF
  • VCCH cavity decoupling capacitors on bottom side: 4x 0603 22µF
    • Option for VCCH: Some 0603 capacitors can be allocated to VCC or VCCIO_PIO/VCCPT depending on power consumption.
    Note: The power tree and number of decoupling capacitors within the cavity on the Agilex™ 7 development kit boards may be slightly different than what has been recommended in this application note due to early release of silicon and guideline. The recommended power tree, guideline, and decoupling capacitors in this application note has been well established and validated by measurement for the final device production.

It is due to reliability to have the cavity area on top layer to be free of components due to OPD in package. However, pads or other coppers are allowed in this area on top layer. This means you can place as much capacitors if they fit into the cavity area on the bottom layer connecting capacitors to top layer through via.

Power Flooding

Altera recommends you to include power flood on the top layer of the board for VCCL. The following example is a good design practice that has shown to reduce the loop inductance by 3x due to a shorter path to FPGA fabric and more effective decoupling solutions.

Figure 6. Example of Board Power Flooding
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